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Searched refs:ccs (Results 1 – 22 of 22) sorted by relevance

/drivers/media/i2c/ccs/
A DMakefile2 ccs-objs += ccs-core.o ccs-reg-access.o \
3 ccs-quirk.o ccs-limits.o ccs-data.o
4 obj-$(CONFIG_VIDEO_CCS) += ccs.o
/drivers/gpu/drm/i915/display/
A Dintel_fb.c234 } ccs; member
260 .ccs.packed_aux_planes = BIT(1),
269 .ccs.packed_aux_planes = BIT(1),
277 .ccs.cc_planes = BIT(2),
278 .ccs.packed_aux_planes = BIT(1),
290 .ccs.cc_planes = BIT(1),
306 .ccs.packed_aux_planes = BIT(1),
315 .ccs.packed_aux_planes = BIT(1),
323 .ccs.cc_planes = BIT(2),
707 if (!md->ccs.cc_planes) in intel_fb_rc_ccs_cc_plane()
[all …]
/drivers/gpu/drm/ci/xfails/
A Di915-amly-fails.txt8 kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc,Timeout
A Di915-whl-fails.txt9 kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc,Timeout
A Di915-cml-fails.txt11 kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc,Timeout
/drivers/gpu/drm/i915/gt/
A Dintel_gt_ccs_mode.c22 if (gt->ccs.cslices & BIT(cslice)) in intel_gt_apply_ccs_mode()
A Dintel_gt_types.h216 } ccs; member
A Dintel_gt_regs.h1429 #define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) argument
A Dintel_engine_cs.c893 gt->ccs.cslices = CCS_MASK(gt); in init_engine_mask()
/drivers/media/i2c/
A DMakefile26 obj-$(CONFIG_VIDEO_CCS) += ccs/
27 obj-$(CONFIG_VIDEO_CCS_PLL) += ccs-pll.o
A DKconfig746 source "drivers/media/i2c/ccs/Kconfig"
/drivers/usb/cdns3/
A Dcdns3-debug.h136 priv_ep->free_trbs, priv_ep->ccs, priv_ep->pcs); in cdns3_dbg_ring()
A Dcdns3-gadget.h1180 u8 ccs; member
A Dcdns3-gadget.c338 cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs); in cdns3_ep_inc_deq()
1517 if ((le32_to_cpu(trb->control) & TRB_CYCLE) != priv_ep->ccs) in cdns3_trb_handled()
2476 priv_ep->ccs = !!EP_STS_CCS(reg); in cdns3_gadget_ep_enable()
/drivers/gpu/drm/xe/regs/
A Dxe_gt_regs.h560 #define CCS_MODE_CSLICE(cslice, ccs) \ argument
561 ((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
/drivers/usb/gadget/udc/cdns2/
A Dcdns2-debug.h124 ring->free_trbs, ring->ccs, ring->pcs); in cdns2_raw_ring()
A Dcdns2-gadget.h520 u8 ccs; member
A Dcdns2-gadget.c195 cdns2_ep_inc_trb(&ring->dequeue, &ring->ccs, TRBS_PER_SEGMENT); in cdns2_ep_inc_deq()
751 if (hw_ccs != pep->ring.ccs) in cdns2_prepare_first_isoc_transfer()
919 if ((le32_to_cpu(trb->control) & TRB_CYCLE) != ring->ccs) in cdns2_trb_handled()
1599 pep->ring.ccs = !!DMA_EP_STS_CCS(reg); in cdns2_gadget_ep_enable()
/drivers/bus/mhi/host/
A Dinternal.h277 enum mhi_ev_ccs ccs; member
A Dmain.c804 mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); in mhi_process_cmd_completion()
1388 if (!ret || mhi_chan->ccs != MHI_EV_CC_SUCCESS) { in mhi_update_channel_state()
A Dinit.c1370 mhi_chan->ccs = MHI_EV_CC_INVALID; in mhi_driver_remove()
/drivers/usb/gadget/udc/
A Dtegra-xudc.c459 bool ccs; member
3113 if (trb_read_cycle(event) != xudc->ccs) in tegra_xudc_process_event_ring()
3126 xudc->ccs = !xudc->ccs; in tegra_xudc_process_event_ring()
3342 xudc->ccs = true; in tegra_xudc_init_event_ring()

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