| /drivers/gpu/drm/i915/display/ |
| A D | intel_cdclk.c | 672 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
761 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
1246 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
1266 display->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1575 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1930 table[i].cdclk == cdclk) in cdclk_squash_waveform()
2252 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2256 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2257 if (cdclk != display->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2289 display->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
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| A D | intel_cdclk.h | 19 unsigned int cdclk, vco, ref, bypass; member
56 …to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->cdclk.…
58 …to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->cdclk.…
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| A D | intel_audio.c | 458 unsigned int fec_coeff, cdclk, vdsc_bppx16; in calc_hblank_early_prog() local
466 cdclk = display->cdclk.hw.cdclk; in calc_hblank_early_prog()
474 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); in calc_hblank_early_prog()
476 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) in calc_hblank_early_prog()
485 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
486 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
917 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) in get_aud_ts_cdclk_m_n() argument
920 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
928 get_aud_ts_cdclk_m_n(display->cdclk.hw.ref, in intel_audio_cdclk_change_post()
929 display->cdclk.hw.cdclk, &aud_ts); in intel_audio_cdclk_change_post()
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| A D | intel_display_core.h | 300 const struct intel_cdclk_funcs *cdclk; member
359 } cdclk; member
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| A D | intel_dsi.c | 68 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dsi_mode_valid()
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| A D | intel_flipq.c | 149 DIV_ROUND_UP(display->cdclk.hw.cdclk * cdclk_factor(display), 540000) + in intel_flipq_exec_time_us()
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| A D | hsw_ips.c | 215 crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100) in hsw_crtc_state_ips_capable()
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| A D | intel_dp_aux.c | 106 freq = display->cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
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| A D | intel_backlight.c | 1114 clock = KHz(display->cdclk.hw.cdclk); in i9xx_hz_to_pwm()
1132 clock = KHz(display->cdclk.hw.cdclk); in i965_hz_to_pwm()
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| A D | intel_display_driver.c | 488 if (display->cdclk.max_cdclk_freq == 0) in intel_display_driver_probe_nogem()
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| A D | intel_dvo.c | 228 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dvo_mode_valid()
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| A D | intel_lvds.c | 399 int max_pixclk = display->cdclk.max_dotclk_freq; in intel_lvds_mode_valid()
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| A D | intel_crt.c | 356 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_crt_mode_valid()
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| A D | intel_dp.c | 909 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / in bigjoiner_bw_max_bpp()
1036 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) in intel_dp_dsc_get_slice_count()
1370 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || in intel_dp_needs_joiner()
1424 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_dp_mode_valid()
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| A D | intel_tv.c | 964 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_tv_mode_valid()
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| A D | intel_display_power_well.c | 1026 intel_cdclk_clock_changed(&display->cdclk.hw, in gen9_disable_dc_states()
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| A D | intel_display.c | 2378 int clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
2394 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; in intel_crtc_compute_pipe_mode()
2402 clock_limit = display->cdclk.max_dotclk_freq; in intel_crtc_compute_pipe_mode()
7908 int max_dotclock = display->cdclk.max_dotclk_freq; in max_dotclock()
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| A D | intel_dp_mst.c | 1456 int max_dotclk = display->cdclk.max_dotclk_freq; in mst_connector_mode_valid_ctx()
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| A D | intel_display_power.c | 1370 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
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| A D | intel_dpll_mgr.c | 1984 display->dpll.ref_clks.nssc = display->cdclk.hw.ref; in skl_update_dpll_ref_clks()
4082 display->dpll.ref_clks.nssc = display->cdclk.hw.ref; in icl_update_dpll_ref_clks()
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| A D | intel_hdmi.c | 2019 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_hdmi_mode_valid()
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| A D | intel_sdvo.c | 1945 int max_dotclk = display->cdclk.max_dotclk_freq; in intel_sdvo_mode_valid()
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| /drivers/clk/samsung/ |
| A D | clk-s5pv210-audss.c | 71 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
106 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
120 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
121 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
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| A D | clk-exynos-audss.c | 129 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
189 cdclk = devm_clk_get(dev, "cdclk"); in exynos_audss_clk_probe()
191 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
192 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
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| /drivers/gpu/drm/i915/ |
| A D | i915_reg.h | 1126 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ argument
1127 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
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