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Searched refs:cdm (Results 1 – 25 of 40) sorted by relevance

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/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_cdm.c170 static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm) in dpu_hw_cdm_enable() argument
177 if (!ctx || !cdm) in dpu_hw_cdm_enable()
180 fmt = cdm->output_fmt; in dpu_hw_cdm_enable()
185 dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true); in dpu_hw_cdm_enable()
186 dpu_hw_cdm_setup_cdwn(ctx, cdm); in dpu_hw_cdm_enable()
188 if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) { in dpu_hw_cdm_enable()
200 ctx->ops.bind_pingpong_blk(ctx, cdm->pp_id); in dpu_hw_cdm_enable()
A Ddpu_hw_cdm.h95 int (*enable)(struct dpu_hw_cdm *cdm, struct dpu_hw_cdm_cfg *cfg);
102 void (*bind_pingpong_blk)(struct dpu_hw_cdm *cdm, const enum dpu_pingpong pp);
126 const struct dpu_cdm_cfg *cdm, void __iomem *addr,
A Ddpu_hw_ctl.c619 if (cfg->cdm) in dpu_hw_ctl_intf_cfg_v1()
620 DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm); in dpu_hw_ctl_intf_cfg_v1()
727 if (cfg->cdm) { in dpu_hw_ctl_reset_intf_cfg_v1()
729 cdm_active &= ~cfg->cdm; in dpu_hw_ctl_reset_intf_cfg_v1()
A Ddpu_hw_ctl.h55 enum dpu_cdm cdm; member
A Ddpu_kms.c673 yuv_supported = !!dpu_kms->catalog->cdm; in _dpu_kms_initialize_displayport()
1057 if (cat->cdm) in dpu_kms_mdp_snapshot()
1058 msm_disp_snapshot_add_block(disp_state, cat->cdm->len, in dpu_kms_mdp_snapshot()
1059 dpu_kms->mmio + cat->cdm->base, in dpu_kms_mdp_snapshot()
1060 "%s", cat->cdm->name); in dpu_kms_mdp_snapshot()
A Ddpu_hw_catalog.h735 const struct dpu_cdm_cfg *cdm; member
/drivers/spi/
A Dspi-ppc4xx.c106 u8 cdm; member
167 u8 cdm = 0; in spi_ppc4xx_setupxfer() local
194 cdm = min(scr, 0xff); in spi_ppc4xx_setupxfer()
196 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); in spi_ppc4xx_setupxfer()
198 if (in_8(&hw->regs->cdm) != cdm) in spi_ppc4xx_setupxfer()
199 out_8(&hw->regs->cdm, cdm); in spi_ppc4xx_setupxfer()
/drivers/net/can/mscan/
A Dmpc5xxx_can.c48 struct mpc52xx_cdm __iomem *cdm; in mpc52xx_can_get_clock() local
81 cdm = of_iomap(np_cdm, 0); in mpc52xx_can_get_clock()
82 if (!cdm) { in mpc52xx_can_get_clock()
88 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
90 val = in_be32(&cdm->rstcfg); in mpc52xx_can_get_clock()
96 iounmap(cdm); in mpc52xx_can_get_clock()
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_cfg.c714 .cdm = {
908 .cdm = {
999 .cdm = {
1085 .cdm = {
1188 .cdm = {
1286 .cdm = {
1384 .cdm = {
A Dmdp5_cfg.h110 struct mdp5_sub_block cdm; member
/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_4_1_sdm670.h132 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_1_15_msm8917.h166 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_1_14_msm8937.h187 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_1_16_msm8953.h194 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_5_4_sm6125.h205 .cdm = &dpu_cdm_5_x,
A Ddpu_6_2_sc7180.h199 .cdm = &dpu_cdm_5_x,
A Ddpu_3_3_sdm630.h202 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_6_4_sm6350.h215 .cdm = &dpu_cdm_5_x,
A Ddpu_5_3_sm6150.h234 .cdm = &dpu_cdm_5_x,
A Ddpu_7_2_sc7280.h239 .cdm = &dpu_cdm_5_x,
A Ddpu_3_2_sdm660.h262 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_1_7_msm8996.h308 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_3_0_msm8998.h298 .cdm = &dpu_cdm_1_x_4_x,
A Ddpu_5_2_sm7150.h293 .cdm = &dpu_cdm_5_x,
A Ddpu_4_0_sdm845.h313 .cdm = &dpu_cdm_1_x_4_x,

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