| /drivers/net/ethernet/mellanox/mlx5/core/en/ |
| A D | htb.c | 279 *max_average_bw = max_t(u32, div_u64(ceil, BYTES_IN_MBIT), 1); in mlx5e_htb_convert_ceil()
282 ceil, *max_average_bw); in mlx5e_htb_convert_ceil()
287 u32 parent_classid, u64 rate, u64 ceil, in mlx5e_htb_leaf_alloc_queue() argument
296 classid, parent_classid, rate, ceil); in mlx5e_htb_leaf_alloc_queue()
314 mlx5e_htb_convert_ceil(htb, ceil, &node->max_average_bw); in mlx5e_htb_leaf_alloc_queue()
343 u64 rate, u64 ceil, struct netlink_ext_ack *extack) in mlx5e_htb_leaf_to_inner() argument
352 classid, child_classid, rate, ceil); in mlx5e_htb_leaf_to_inner()
377 mlx5e_htb_convert_ceil(htb, ceil, &child->max_average_bw); in mlx5e_htb_leaf_to_inner()
655 mlx5e_htb_node_modify(struct mlx5e_htb *htb, u16 classid, u64 rate, u64 ceil, in mlx5e_htb_node_modify() argument
664 classid, rate, ceil); in mlx5e_htb_node_modify()
[all …]
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| A D | htb.h | 26 u32 parent_classid, u64 rate, u64 ceil,
30 u64 rate, u64 ceil, struct netlink_ext_ack *extack);
37 mlx5e_htb_node_modify(struct mlx5e_htb *htb, u16 classid, u64 rate, u64 ceil,
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| A D | qos.c | 425 htb_qopt->rate, htb_qopt->ceil, htb_qopt->extack); in mlx5e_htb_setup_tc()
432 htb_qopt->rate, htb_qopt->ceil, htb_qopt->extack); in mlx5e_htb_setup_tc()
441 return mlx5e_htb_node_modify(htb, htb_qopt->classid, htb_qopt->rate, htb_qopt->ceil, in mlx5e_htb_setup_tc()
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| /drivers/iio/light/ |
| A D | lv0104cs.c | 278 int floor, ceil, mid; in lv0104cs_set_calibscale() local
285 ceil = lv0104cs_calibscales[i + 1].val * 1000000 in lv0104cs_set_calibscale()
287 mid = (floor + ceil) / 2; in lv0104cs_set_calibscale()
296 if (calibscale >= mid && calibscale <= ceil) { in lv0104cs_set_calibscale()
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| /drivers/net/ethernet/marvell/octeontx2/nic/ |
| A D | qos.c | 119 maxrate = (node->rate > node->ceil) ? node->rate : node->ceil; in otx2_config_sched_shaping()
475 txschq_node->ceil = 0; in otx2_qos_alloc_txschq_node()
505 u16 classid, u32 prio, u64 rate, u64 ceil, in otx2_qos_sw_create_leaf_node() argument
521 node->ceil = otx2_convert_rate(ceil); in otx2_qos_sw_create_leaf_node()
1223 u32 parent_classid, u64 rate, u64 ceil, in otx2_qos_leaf_alloc_queue() argument
1303 ceil, quantum, qid, static_cfg); in otx2_qos_leaf_alloc_queue()
1362 u16 child_classid, u64 rate, u64 ceil, u64 prio, in otx2_qos_leaf_to_inner() argument
1373 classid, child_classid, rate, ceil); in otx2_qos_leaf_to_inner()
1439 prio, rate, ceil, quantum, in otx2_qos_leaf_to_inner()
1746 htb->rate, htb->ceil, in otx2_setup_tc_htb()
[all …]
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| A D | qos.h | 60 u64 ceil; member
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| /drivers/char/ |
| A D | random.c | 557 u32 __get_random_u32_below(u32 ceil) in DEFINE_BATCHED_ENTROPY()
579 if (unlikely(!ceil)) in DEFINE_BATCHED_ENTROPY()
582 mult = (u64)ceil * rand; in DEFINE_BATCHED_ENTROPY()
583 if (unlikely((u32)mult < ceil)) { in DEFINE_BATCHED_ENTROPY()
584 u32 bound = -ceil % ceil; in DEFINE_BATCHED_ENTROPY()
586 mult = (u64)ceil * get_random_u32(); in DEFINE_BATCHED_ENTROPY()
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| /drivers/ufs/host/ |
| A D | ufs-qcom.h | 312 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1)) macro
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| A D | ufs-qcom.c | 1458 cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1472 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1477 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1479 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_util.c | 186 double ceil = dml_ceil(val, 1); in dml_round() local
190 return ceil; in dml_round()
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| /drivers/media/tuners/ |
| A D | mt2063.c | 354 #define ceil(n, d) (((n) < 0) ? (-((-(n))/(d))) : (n)/(d) + ((n)%(d) != 0)) macro
612 ceil((s32) (pNode->max_ - f_Center), (s32) f_Step); in MT2063_ChooseFirstIF()
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