| /drivers/of/unittest-data/ |
| A D | tests-address.dtsi | 4 #address-cells = <1>;
5 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <1>;
27 #size-cells = <2>;
39 #size-cells = <2>;
48 #size-cells = <2>;
57 #size-cells = <1>;
[all …]
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| A D | tests-interrupts.dtsi | 6 #address-cells = <1>;
7 #size-cells = <1>;
11 #interrupt-cells = <1>;
16 #interrupt-cells = <3>;
21 #interrupt-cells = <2>;
25 #interrupt-cells = <1>;
26 #address-cells = <0>;
34 #interrupt-cells = <2>;
48 #address-cells = <1>;
54 #interrupt-cells = <1>;
[all …]
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| A D | tests-platform.dtsi | 6 #address-cells = <1>;
7 #size-cells = <0>;
13 #address-cells = <1>;
14 #size-cells = <0>;
26 #address-cells = <1>;
27 #size-cells = <0>;
54 // No #address-cells or #size-cells
56 #address-cells = <1>;
57 #size-cells = <1>;
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| A D | tests-overlay.dtsi | 9 #address-cells = <1>;
10 #size-cells = <0>;
77 #address-cells = <1>;
78 #size-cells = <0>;
97 #address-cells = <1>;
98 #size-cells = <0>;
101 #address-cells = <1>;
102 #size-cells = <0>;
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| A D | overlay_15.dtso | 8 #address-cells = <1>;
9 #size-cells = <0>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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| A D | overlay.dtso | 17 #address-cells = <1>;
18 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <1>;
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| A D | tests-phandle.dtsi | 16 #phandle-cells = <0>;
20 #phandle-cells = <1>;
24 #phandle-cells = <2>;
28 #phandle-cells = <3>;
32 #phandle-cells = <2>;
44 #phandle-cells = <2>;
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| A D | overlay_common.dtsi | 14 #address-cells = <1>;
15 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <1>;
47 #address-cells = <1>;
48 #size-cells = <1>;
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| A D | overlay_pci_node.dtso | 7 #address-cells = <3>;
8 #size-cells = <2>;
11 #address-cells = <1>;
12 #size-cells = <1>;
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| A D | overlay_10.dtso | 10 #address-cells = <1>;
11 #size-cells = <0>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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| A D | overlay_11.dtso | 10 #address-cells = <1>;
11 #size-cells = <0>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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| /drivers/misc/ |
| A D | lan966x_pci.dtso | 25 #interrupt-cells = <1>;
29 #address-cells = <3>;
30 #size-cells = <2>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #address-cells = <1>;
53 #size-cells = <1>;
90 #gpio-cells = <2>;
114 #phy-cells = <2>;
[all …]
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| /drivers/mfd/ |
| A D | sky81452.c | 28 struct mfd_cell cells[2]; in sky81452_probe() local
46 memset(cells, 0, sizeof(cells)); in sky81452_probe()
47 cells[0].name = "sky81452-backlight"; in sky81452_probe()
48 cells[0].of_compatible = "skyworks,sky81452-backlight"; in sky81452_probe()
49 cells[1].name = "sky81452-regulator"; in sky81452_probe()
50 cells[1].platform_data = pdata->regulator_init_data; in sky81452_probe()
51 cells[1].pdata_size = sizeof(*pdata->regulator_init_data); in sky81452_probe()
53 ret = devm_mfd_add_devices(dev, -1, cells, ARRAY_SIZE(cells), in sky81452_probe()
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| A D | lpc_sch.c | 137 unsigned int cells = 0; in lpc_sch_probe() local
142 id->device, &lpc_sch_cells[cells]); in lpc_sch_probe()
146 cells++; in lpc_sch_probe()
150 id->device, &lpc_sch_cells[cells]); in lpc_sch_probe()
154 cells++; in lpc_sch_probe()
158 id->device, &lpc_sch_cells[cells]); in lpc_sch_probe()
162 cells++; in lpc_sch_probe()
164 if (cells == 0) { in lpc_sch_probe()
169 return mfd_add_devices(&dev->dev, 0, lpc_sch_cells, cells, NULL, 0, NULL); in lpc_sch_probe()
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| A D | rsmu_core.c | 54 struct mfd_cell *cells; in rsmu_core_init() local
59 cells = rsmu_cm_devs; in rsmu_core_init()
62 cells = rsmu_sabre_devs; in rsmu_core_init()
65 cells = rsmu_sl_devs; in rsmu_core_init()
74 ret = devm_mfd_add_devices(rsmu->dev, PLATFORM_DEVID_AUTO, cells, in rsmu_core_init()
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| A D | wm97xx-core.c | 256 struct mfd_cell *cells; in wm97xx_ac97_probe() local
282 cells = wm9705_cells; in wm97xx_ac97_probe()
287 cells = wm9712_cells; in wm97xx_ac97_probe()
292 cells = wm9713_cells; in wm97xx_ac97_probe()
300 cells[i].platform_data = codec_pdata; in wm97xx_ac97_probe()
301 cells[i].pdata_size = sizeof(*codec_pdata); in wm97xx_ac97_probe()
311 cells, nb_cells, NULL, 0, NULL); in wm97xx_ac97_probe()
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| A D | mt6397-core.c | 285 const struct mfd_cell *cells; member
293 .cells = mt6323_devs,
301 .cells = mt6328_devs,
309 .cells = mt6357_devs,
317 .cells = mt6331_mt6332_devs,
325 .cells = mt6358_devs,
333 .cells = mt6359_devs,
341 .cells = mt6397_devs,
390 pmic_core->cells, pmic_core->cell_size, in mt6397_probe()
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| /drivers/platform/x86/intel/int3472/ |
| A D | tps68470.c | 148 struct mfd_cell *cells; in skl_int3472_tps68470_probe() local
183 cells = kcalloc(TPS68470_WIN_MFD_CELL_COUNT, sizeof(*cells), GFP_KERNEL); in skl_int3472_tps68470_probe()
184 if (!cells) in skl_int3472_tps68470_probe()
193 cells[0].name = "tps68470-clk"; in skl_int3472_tps68470_probe()
194 cells[0].platform_data = clk_pdata; in skl_int3472_tps68470_probe()
195 cells[0].pdata_size = struct_size(clk_pdata, consumers, n_consumers); in skl_int3472_tps68470_probe()
196 cells[1].name = "tps68470-regulator"; in skl_int3472_tps68470_probe()
197 cells[1].platform_data = (void *)board_data->tps68470_regulator_pdata; in skl_int3472_tps68470_probe()
199 cells[2].name = "tps68470-gpio"; in skl_int3472_tps68470_probe()
205 cells, TPS68470_WIN_MFD_CELL_COUNT, in skl_int3472_tps68470_probe()
[all …]
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| /drivers/clk/ |
| A D | clk-eyeq.c | 255 cells->hws[pll->index] = hw; in eqc_probe_init_plls()
289 cells->hws[div->index] = hw; in eqc_probe_init_divs()
318 cells->hws[ff->index] = hw; in eqc_probe_init_fixed_factors()
403 cells = kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL); in eqc_probe()
404 if (!cells) in eqc_probe()
407 cells->num = clk_count; in eqc_probe()
741 cells = kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL); in eqc_early_init()
742 if (!cells) { in eqc_early_init()
747 cells->num = clk_count; in eqc_early_init()
826 if (cells) { in eqc_early_init()
[all …]
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| /drivers/nvmem/ |
| A D | brcm_nvram.c | 37 struct nvmem_cell_info *cells; member
136 priv->cells = devm_kcalloc(dev, priv->ncells, sizeof(*priv->cells), GFP_KERNEL); in brcm_nvram_add_cells()
137 if (!priv->cells) { in brcm_nvram_add_cells()
159 priv->cells[idx].name = name; in brcm_nvram_add_cells()
160 priv->cells[idx].offset = value - (char *)data; in brcm_nvram_add_cells()
161 priv->cells[idx].bytes = strlen(value); in brcm_nvram_add_cells()
162 priv->cells[idx].np = of_get_child_by_name(dev->of_node, priv->cells[idx].name); in brcm_nvram_add_cells()
166 priv->cells[idx].raw_len = strlen(value); in brcm_nvram_add_cells()
167 priv->cells[idx].bytes = ETH_ALEN; in brcm_nvram_add_cells()
168 priv->cells[idx].read_post_process = brcm_nvram_read_post_process_macaddr; in brcm_nvram_add_cells()
[all …]
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| /drivers/of/ |
| A D | empty_root.dts | 6 * #address-cells/#size-cells are required properties at root node.
7 * Use 2 cells for both address cells and size cells in order to fully
11 #address-cells = <0x02>;
12 #size-cells = <0x02>;
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| /drivers/clk/mmp/ |
| A D | clk-of-pxa910.c | 236 struct mmp_clk_reset_cell *cells; in pxa910_clk_reset_init() local
242 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); in pxa910_clk_reset_init()
243 if (!cells) in pxa910_clk_reset_init()
248 cells[base + i].clk_id = apbc_gate_clks[i].id; in pxa910_clk_reset_init()
249 cells[base + i].reg = in pxa910_clk_reset_init()
251 cells[base + i].flags = 0; in pxa910_clk_reset_init()
253 cells[base + i].bits = 0x4; in pxa910_clk_reset_init()
259 cells[base + i].reg = in pxa910_clk_reset_init()
261 cells[base + i].flags = 0; in pxa910_clk_reset_init()
263 cells[base + i].bits = 0x4; in pxa910_clk_reset_init()
[all …]
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| A D | clk-of-pxa1928.c | 186 struct mmp_clk_reset_cell *cells; in pxa1928_clk_reset_init() local
190 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); in pxa1928_clk_reset_init()
191 if (!cells) in pxa1928_clk_reset_init()
196 cells[base + i].clk_id = apbc_gate_clks[i].id; in pxa1928_clk_reset_init()
197 cells[base + i].reg = in pxa1928_clk_reset_init()
199 cells[base + i].flags = 0; in pxa1928_clk_reset_init()
200 cells[base + i].lock = apbc_gate_clks[i].lock; in pxa1928_clk_reset_init()
201 cells[base + i].bits = 0x4; in pxa1928_clk_reset_init()
204 mmp_clk_reset_register(np, cells, nr_resets); in pxa1928_clk_reset_init()
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| A D | reset.c | 23 cell = &unit->cells[i]; in mmp_of_reset_xlate()
42 cell = &unit->cells[id]; in mmp_clk_reset_assert()
64 cell = &unit->cells[id]; in mmp_clk_reset_deassert()
84 struct mmp_clk_reset_cell *cells, int nr_resets) in mmp_clk_reset_register() argument
92 unit->cells = cells; in mmp_clk_reset_register()
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| A D | clk-of-pxa168.c | 281 struct mmp_clk_reset_cell *cells; in pxa168_clk_reset_init() local
285 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); in pxa168_clk_reset_init()
286 if (!cells) in pxa168_clk_reset_init()
290 cells[i].clk_id = apbc_gate_clks[i].id; in pxa168_clk_reset_init()
291 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; in pxa168_clk_reset_init()
292 cells[i].flags = 0; in pxa168_clk_reset_init()
293 cells[i].lock = apbc_gate_clks[i].lock; in pxa168_clk_reset_init()
294 cells[i].bits = 0x4; in pxa168_clk_reset_init()
297 mmp_clk_reset_register(np, cells, nr_resets); in pxa168_clk_reset_init()
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