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Searched refs:cfg1 (Results 1 – 25 of 41) sorted by relevance

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/drivers/spi/
A Dspi-qpic-snand.c592 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_last_cw()
727 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_cw_raw()
836 cfg1 = ecc_cfg->cfg1; in qcom_spi_read_page_ecc()
843 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_page_ecc()
929 cfg1 = ecc_cfg->cfg1; in qcom_spi_read_page_oob()
936 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_read_page_oob()
1057 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_raw()
1123 cfg1 = ecc_cfg->cfg1; in qcom_spi_program_ecc()
1141 snandc->regs->cfg1 = cpu_to_le32(cfg1); in qcom_spi_program_ecc()
1200 cfg1 = ecc_cfg->cfg1; in qcom_spi_program_oob()
[all …]
/drivers/usb/typec/mux/
A Dps883x.c62 int cfg1, int cfg2) in ps883x_configure() argument
73 ret = regmap_write(retimer->regmap, REG_USB_PORT_CONN_STATUS_1, cfg1); in ps883x_configure()
91 int cfg1 = 0x00; in ps883x_set() local
96 return ps883x_configure(retimer, cfg0, cfg1, cfg2); in ps883x_set()
111 cfg1 = CONN_STATUS_1_DP_CONNECTED | in ps883x_set()
119 cfg1 = CONN_STATUS_1_DP_CONNECTED | in ps883x_set()
126 cfg1 = CONN_STATUS_1_DP_CONNECTED | in ps883x_set()
134 return ps883x_configure(retimer, cfg0, cfg1, cfg2); in ps883x_set()
/drivers/comedi/drivers/
A Dni_at_ao.c106 unsigned short cfg1; member
118 devpriv->cfg1 |= ATAO_CFG1_GRP2WR; in atao_select_reg_group()
120 devpriv->cfg1 &= ~ATAO_CFG1_GRP2WR; in atao_select_reg_group()
121 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_select_reg_group()
269 devpriv->cfg1 = 0; in atao_reset()
270 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_reset()
/drivers/gpu/drm/exynos/
A Dexynos_drm_fimc.c419 u32 cfg1, cfg2; in fimc_src_set_transf() local
423 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); in fimc_src_set_transf()
424 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf()
433 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
435 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
440 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; in fimc_src_set_transf()
442 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; in fimc_src_set_transf()
445 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | in fimc_src_set_transf()
463 fimc_write(ctx, cfg1, EXYNOS_MSCTRL); in fimc_src_set_transf()
1011 u32 cfg0, cfg1; in fimc_start() local
[all …]
/drivers/clk/thead/
A Dclk-th1520-ap.c40 u16 cfg1; member
250 unsigned int cfg0, cfg1; in th1520_pll_vco_recalc_rate() local
254 regmap_read(pll->common.map, pll->common.cfg1, &cfg1); in th1520_pll_vco_recalc_rate()
277 regmap_read(pll->common.map, pll->common.cfg1, &cfg1); in th1520_pll_postdiv_recalc_rate()
313 .cfg1 = 0x004,
325 .cfg1 = 0x014,
337 .cfg1 = 0x024,
357 .cfg1 = 0x034,
377 .cfg1 = 0x044,
393 .cfg1 = 0x054,
[all …]
/drivers/gpu/drm/nouveau/dispnv04/
A Darb.c202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); in nv04_update_arb() local
225 sim_data.mem_latency = cfg1 & 0xf; in nv04_update_arb()
226 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); in nv04_update_arb()
/drivers/media/platform/atmel/
A Datmel-isi.c360 u32 ctrl, cfg1; in start_dma() local
362 cfg1 = isi_readl(isi, ISI_CFG1); in start_dma()
387 cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK; in start_dma()
398 isi_writel(isi, ISI_CFG1, cfg1); in start_dma()
793 u32 cfg1 = 0; in isi_camera_set_bus_param() local
798 cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param()
800 cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW; in isi_camera_set_bus_param()
804 cfg1 |= ISI_CFG1_EMB_SYNC; in isi_camera_set_bus_param()
806 cfg1 |= ISI_CFG1_FULL_MODE; in isi_camera_set_bus_param()
808 cfg1 |= ISI_CFG1_THMASK_BEATS_16; in isi_camera_set_bus_param()
[all …]
/drivers/net/wireless/realtek/rtw89/
A Dpci_be.c411 u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy; in rtw89_pci_ltr_set_v2() local
419 cfg1 = rtw89_read32(rtwdev, R_BE_LTR_CFG_1); in rtw89_pci_ltr_set_v2()
420 if (rtw89_pci_ltr_is_err_reg_val(cfg1)) in rtw89_pci_ltr_set_v2()
448 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK); in rtw89_pci_ltr_set_v2()
449 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK); in rtw89_pci_ltr_set_v2()
459 rtw89_write32(rtwdev, R_BE_LTR_CFG_1, cfg1); in rtw89_pci_ltr_set_v2()
/drivers/net/wireless/mediatek/mt76/mt76x2/
A Dphy.c187 u32 cfg0, cfg1; in mt76x2_configure_tx_delay() local
191 cfg1 = 0x00011414; in mt76x2_configure_tx_delay()
194 cfg1 = 0x00021414; in mt76x2_configure_tx_delay()
197 mt76_wr(dev, MT_TX_SW_CFG1, cfg1); in mt76x2_configure_tx_delay()
/drivers/iio/adc/
A Dimx7d_adc.c236 u32 cfg1 = 0; in imx7d_adc_channel_set() local
243 cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN | in imx7d_adc_channel_set()
253 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel); in imx7d_adc_channel_set()
270 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel); in imx7d_adc_channel_set()
/drivers/infiniband/hw/erdma/
A Derdma_hw.h260 u32 cfg1; member
286 u32 cfg1; member
358 u32 cfg1; member
412 u32 cfg1; member
A Derdma_verbs.c54 req.cfg1 = FIELD_PREP(ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK, in create_qp_cmd()
163 req.cfg1 = FIELD_PREP(ERDMA_CMD_REGMR_PD_MASK, pd->pdn) | in regmr_cmd()
204 req.cfg1 = FIELD_PREP(ERDMA_CMD_CREATE_CQ_EQN_MASK, cq->assoc_eqn); in create_cq_cmd()
213 req.cfg1 |= FIELD_PREP(ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK, 1) | in create_cq_cmd()
227 req.cfg1 |= in create_cq_cmd()
233 req.cfg1 |= in create_cq_cmd()
237 req.cfg1 |= FIELD_PREP(ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK, in create_cq_cmd()
244 req.cfg1 |= FIELD_PREP( in create_cq_cmd()
/drivers/perf/
A Dfsl_imx8_ddr_perf.c556 int cfg1 = event->attr.config1; in ddr_perf_event_add() local
570 cfg1 ^= AXI_MASKING_REVERT; in ddr_perf_event_add()
571 writel(cfg1, pmu->base + COUNTER_DPCR1); in ddr_perf_event_add()
584 cfg1 ^= AXI_MASKING_REVERT; in ddr_perf_event_add()
585 writel(cfg1, pmu->base + COUNTER_MASK_COMP + ((counter - 1) << 4)); in ddr_perf_event_add()
A Dfsl_imx9_ddr_perf.c628 int cfg1 = event->attr.config1; in ddr_perf_event_add() local
648 imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); in ddr_perf_event_add()
652 imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); in ddr_perf_event_add()
/drivers/video/fbdev/nvidia/
A Dnv_hw.c387 unsigned int MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
397 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings()
400 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings()
626 unsigned int MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
637 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings()
640 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
/drivers/net/ethernet/agere/
A Det131x.c819 &macregs->cfg1); in et1310_config_mac_regs1()
861 writel(0, &macregs->cfg1); in et1310_config_mac_regs1()
869 u32 cfg1; in et1310_config_mac_regs2() local
875 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
894 cfg1 |= ET_MAC_CFG1_RX_FLOW; in et1310_config_mac_regs2()
895 writel(cfg1, &mac->cfg1); in et1310_config_mac_regs2()
921 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
927 cfg1); in et1310_config_mac_regs2()
1689 writel(reg, &adapter->regs->mac.cfg1); in et131x_soft_reset()
1696 writel(reg, &adapter->regs->mac.cfg1); in et131x_soft_reset()
[all …]
A Det131x.h1047 u32 cfg1; /* 0x5000 */ member
/drivers/soc/qcom/
A Dqcom-geni-se.c433 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; in geni_se_config_packing() local
462 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT); in geni_se_config_packing()
466 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
470 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
/drivers/mtd/nand/raw/
A Dqcom_nandc.c110 u32 cfg0, cfg1; member
261 __le32 cmd, cfg0, cfg1, ecc_bch_cfg; in update_rw_regs() local
277 cfg1 = cpu_to_le32(host->cfg1); in update_rw_regs()
283 cfg1 = cpu_to_le32(host->cfg1_raw); in update_rw_regs()
289 nandc->regs->cfg1 = cfg1; in update_rw_regs()
1506 host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | in qcom_nand_attach_chip()
1545 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_attach_chip()
1821 nandc->regs->cfg1 = cpu_to_le32(host->cfg1_raw); in qcom_misc_cmd_type_exec()
1894 nandc->regs->cfg1 = cpu_to_le32(FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) | in qcom_param_page_type_exec()
/drivers/phy/qualcomm/
A Dphy-qcom-edp.c747 u8 cfg1; in qcom_edp_phy_power_on() local
826 cfg1 = 0x1; in qcom_edp_phy_power_on()
832 cfg1 = 0x3; in qcom_edp_phy_power_on()
838 cfg1 = 0xf; in qcom_edp_phy_power_on()
845 writel(cfg1, edp->edp + DP_PHY_CFG_1); in qcom_edp_phy_power_on()
/drivers/video/fbdev/riva/
A Driva_hw.c802 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
810 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings()
816 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv4UpdateArbitrationSettings()
818 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv4UpdateArbitrationSettings()
1051 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
1059 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings()
1067 sim_data.mem_latency = (char)cfg1 & 0x0F; in nv10UpdateArbitrationSettings()
1069 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); in nv10UpdateArbitrationSettings()
/drivers/scsi/
A Dqla1280.c2179 uint16_t hwrev, cfg1, cdma_conf; in qla1280_nvram_config() local
2183 cfg1 = RD_REG_WORD(&reg->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()
2188 cfg1 |= nv->isp_config.fifo_threshold << 4; in qla1280_nvram_config()
2190 cfg1 |= nv->isp_config.burst_enable << 2; in qla1280_nvram_config()
2191 WRT_REG_WORD(&reg->cfg_1, cfg1); in qla1280_nvram_config()
2196 uint16_t cfg1, term; in qla1280_nvram_config() local
2199 cfg1 = nv->isp_config.fifo_threshold << 4; in qla1280_nvram_config()
2200 cfg1 |= nv->isp_config.burst_enable << 2; in qla1280_nvram_config()
2203 cfg1 |= BIT_13; in qla1280_nvram_config()
2204 WRT_REG_WORD(&reg->cfg_1, cfg1); in qla1280_nvram_config()
/drivers/net/ethernet/atheros/
A Dag71xx.c1022 u32 cfg1, cfg2; in ag71xx_mac_link_up() local
1056 cfg1 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG1); in ag71xx_mac_link_up()
1057 cfg1 &= ~(MAC_CFG1_TFC | MAC_CFG1_RFC); in ag71xx_mac_link_up()
1059 cfg1 |= MAC_CFG1_TFC; in ag71xx_mac_link_up()
1062 cfg1 |= MAC_CFG1_RFC; in ag71xx_mac_link_up()
1063 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1); in ag71xx_mac_link_up()
/drivers/pci/controller/
A Dpcie-altera.c380 u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1; in get_tlp_header() local
384 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1; in get_tlp_header()
386 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1; in get_tlp_header()
/drivers/net/ethernet/smsc/
A Dsmc91x.c907 int bmcr, cfg1; in smc_phy_fixed() local
912 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); in smc_phy_fixed()
913 cfg1 |= PHY_CFG1_LNKDIS; in smc_phy_fixed()
914 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); in smc_phy_fixed()

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