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Searched refs:cfg_addr (Results 1 – 9 of 9) sorted by relevance

/drivers/char/hw_random/
A Dmeson-rng.c45 static int meson_rng_wait_status(void __iomem *cfg_addr, int bit) in meson_rng_wait_status() argument
50 ret = readl_relaxed_poll_timeout_atomic(cfg_addr, in meson_rng_wait_status()
64 void __iomem *cfg_addr = data->base + RNG_S4_CFG; in meson_s4_rng_read() local
67 writel_relaxed(readl_relaxed(cfg_addr) | SEED_READY_STS_BIT, cfg_addr); in meson_s4_rng_read()
69 err = meson_rng_wait_status(cfg_addr, SEED_READY_STS_BIT); in meson_s4_rng_read()
75 err = meson_rng_wait_status(cfg_addr, RUN_BIT); in meson_s4_rng_read()
/drivers/regulator/
A Dmax77620-regulator.c64 u8 cfg_addr; member
218 addr = rinfo->cfg_addr; in max77620_regulator_set_power_mode()
247 addr = rinfo->cfg_addr; in max77620_regulator_get_power_mode()
271 ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &rval); in max77620_read_slew_rate()
274 rinfo->cfg_addr, ret); in max77620_read_slew_rate()
373 rinfo->cfg_addr, ret); in max77620_config_power_ok()
521 ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, in max77620_regulator_set_mode()
525 rinfo->cfg_addr, ret); in max77620_regulator_set_mode()
560 rinfo->cfg_addr, ret); in max77620_regulator_get_mode()
665 .cfg_addr = MAX77620_REG_##_id##_CFG, \
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/drivers/ata/
A Dsata_uli.c96 unsigned int cfg_addr = get_scr_cfg_addr(link->ap, sc_reg); in uli_scr_cfg_read() local
99 pci_read_config_dword(pdev, cfg_addr, &val); in uli_scr_cfg_read()
106 unsigned int cfg_addr = get_scr_cfg_addr(link->ap, scr); in uli_scr_cfg_write() local
108 pci_write_config_dword(pdev, cfg_addr, val); in uli_scr_cfg_write()
A Dsata_sis.c132 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); in sis_scr_cfg_read() local
137 pci_read_config_dword(pdev, cfg_addr, val); in sis_scr_cfg_read()
145 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); in sis_scr_cfg_write() local
147 pci_write_config_dword(pdev, cfg_addr, val); in sis_scr_cfg_write()
/drivers/pci/controller/
A Dpci-xgene.c66 unsigned long cfg_addr; member
356 port->cfg_addr = res->start; in xgene_pcie_map_reg()
395 u64 addr = port->cfg_addr; in xgene_pcie_setup_cfg_reg()
A Dpci-hyperv.c507 void __iomem *cfg_addr; member
1219 void __iomem *addr = hbus->cfg_addr + offset; in _hv_pcifront_read_config()
1222 writel(hpdev->desc.win_slot.slot, hbus->cfg_addr); in _hv_pcifront_read_config()
1268 void __iomem *addr = hbus->cfg_addr + CFG_PAGE_OFFSET + in hv_pcifront_get_vendor_id()
1271 writel(hpdev->desc.win_slot.slot, hbus->cfg_addr); in hv_pcifront_get_vendor_id()
1315 void __iomem *addr = hbus->cfg_addr + offset; in _hv_pcifront_write_config()
1318 writel(hpdev->desc.win_slot.slot, hbus->cfg_addr); in _hv_pcifront_write_config()
3850 hbus->cfg_addr = ioremap(hbus->mem_config->start, in hv_pci_probe()
3852 if (!hbus->cfg_addr) { in hv_pci_probe()
3916 iounmap(hbus->cfg_addr); in hv_pci_probe()
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/drivers/iommu/
A Dfsl_pamu_domain.c377 version = in_be32(pci_ctl->cfg_addr + (PCI_FSL_BRR1 >> 2)); in check_pci_ctl_endpt_part()
/drivers/net/ethernet/huawei/hinic/
A Dhinic_hw_dev.h411 u32 cfg_addr; member
/drivers/net/ethernet/chelsio/cxgb4/
A Dt4_hw.c10165 int ret, i, n, cfg_addr; in t4_load_cfg() local
10170 cfg_addr = t4_flash_cfg_addr(adap); in t4_load_cfg()
10171 if (cfg_addr < 0) in t4_load_cfg()
10172 return cfg_addr; in t4_load_cfg()
10174 addr = cfg_addr; in t4_load_cfg()
10713 int ret, i, n, cfg_addr; in t4_load_bootcfg() local
10715 cfg_addr = t4_flash_bootcfg_addr(adap); in t4_load_bootcfg()
10716 if (cfg_addr < 0) in t4_load_bootcfg()
10717 return cfg_addr; in t4_load_bootcfg()
10719 addr = cfg_addr; in t4_load_bootcfg()
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