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Searched refs:cfg_base (Results 1 – 12 of 12) sorted by relevance

/drivers/net/can/sja1000/
A Dpeak_pci.c459 card->cfg_base = chan->cfg_base; in peak_pciec_probe()
556 void __iomem *cfg_base, *reg_base; in peak_pci_probe() local
590 if (!cfg_base) { in peak_pci_probe()
628 icr = readw(cfg_base + PITA_ICR + 2); in peak_pci_probe()
640 chan->cfg_base = cfg_base; in peak_pci_probe()
695 writew(icr, cfg_base + PITA_ICR + 2); in peak_pci_probe()
705 writew(0x0, cfg_base + PITA_ICR + 2); in peak_pci_probe()
724 pci_iounmap(pdev, cfg_base); in peak_pci_probe()
744 void __iomem *cfg_base = chan->cfg_base; in peak_pci_remove() local
748 writew(0x0, cfg_base + PITA_ICR + 2); in peak_pci_remove()
[all …]
/drivers/perf/
A Dalibaba_uncore_drw_pmu.c94 void __iomem *cfg_base; member
293 return readl(drw_pmu->cfg_base + in ali_drw_pmu_read_counter()
323 drw_pmu->cfg_base + ALI_DRW_PMU_TEST_CTRL); in ali_drw_pmu_event_set_period()
341 val = readl(drw_pmu->cfg_base + reg); in ali_drw_pmu_enable_counter()
349 writel(val, drw_pmu->cfg_base + reg); in ali_drw_pmu_enable_counter()
359 val = readl(drw_pmu->cfg_base + reg); in ali_drw_pmu_disable_counter()
367 writel(val, drw_pmu->cfg_base + reg); in ali_drw_pmu_disable_counter()
580 drw_pmu->cfg_base + ALI_DRW_PMU_CNT_CTRL); in ali_drw_pmu_start()
589 drw_pmu->cfg_base + ALI_DRW_PMU_CNT_PRELOAD); in ali_drw_pmu_start()
679 if (IS_ERR(drw_pmu->cfg_base)) in ali_drw_pmu_probe()
[all …]
A Dmarvell_cn10k_ddr_pmu.c176 u64 cfg_base; member
539 reg = DDRC_PERF_CFG(p_data->cfg_base, counter); in cn10k_ddr_perf_counter_enable()
644 reg_offset = DDRC_PERF_CFG(p_data->cfg_base, counter); in cn10k_ddr_perf_event_add()
945 .cfg_base = CN10K_DDRC_PERF_CFG_BASE,
972 .cfg_base = ODY_DDRC_PERF_CFG_BASE,
/drivers/pci/controller/
A Dpci-xgene.c65 void __iomem *cfg_base; member
106 return port->cfg_base + AXI_EP_CFG_ACCESS; in xgene_pcie_get_cfg_base()
108 return port->cfg_base; in xgene_pcie_get_cfg_base()
244 port->cfg_base = cfg->win; in xgene_pcie_ecam_init()
353 port->cfg_base = devm_ioremap_resource(dev, res); in xgene_pcie_map_reg()
354 if (IS_ERR(port->cfg_base)) in xgene_pcie_map_reg()
355 return PTR_ERR(port->cfg_base); in xgene_pcie_map_reg()
480 void __iomem *cfg_base = port->cfg_base; in xgene_pcie_setup_ib_reg() local
505 bar_addr = cfg_base + PCI_BASE_ADDRESS_0; in xgene_pcie_setup_ib_reg()
A Dpcie-xilinx-dma-pl.c120 void __iomem *cfg_base; member
201 return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in xilinx_pl_dma_pcie_map_bus()
748 port->cfg_base = port->cfg->win; in xilinx_pl_dma_pcie_parse_dt()
/drivers/pci/controller/dwc/
A Dpci-meson.c68 void __iomem *cfg_base; member
116 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); in meson_pcie_get_mems()
117 if (IS_ERR(mp->cfg_base)) in meson_pcie_get_mems()
118 return PTR_ERR(mp->cfg_base); in meson_pcie_get_mems()
223 return readl(mp->cfg_base + reg); in meson_cfg_readl()
228 writel(val, mp->cfg_base + reg); in meson_cfg_writel()
/drivers/gpu/drm/i915/gvt/
A Dcfg_space.c72 u8 *cfg_base = vgpu_cfg_space(vgpu); in vgpu_pci_cfg_mem_write() local
79 old = cfg_base[off + i]; in vgpu_pci_cfg_mem_write()
90 cfg_base[off + i] = (old & ~mask) | new; in vgpu_pci_cfg_mem_write()
95 memcpy(cfg_base + off + i, src + i, bytes - i); in vgpu_pci_cfg_mem_write()
/drivers/soc/ti/
A Dpruss.c348 reg = pruss->cfg_base + reg_offset; in pruss_clk_mux_setup()
481 pruss->cfg_base = devm_ioremap(dev, res.start, resource_size(&res)); in pruss_cfg_of_init()
482 if (!pruss->cfg_base) in pruss_cfg_of_init()
489 pruss->cfg_regmap = devm_regmap_init_mmio(dev, pruss->cfg_base, in pruss_cfg_of_init()
/drivers/pci/controller/cadence/
A Dpcie-cadence-host.c74 return rc->cfg_base + (where & 0xfff); in cdns_pci_map_bus()
662 rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); in cdns_pcie_host_setup()
663 if (IS_ERR(rc->cfg_base)) in cdns_pcie_host_setup()
664 return PTR_ERR(rc->cfg_base); in cdns_pcie_host_setup()
A Dpcie-cadence.h300 void __iomem *cfg_base; member
/drivers/net/ethernet/tehuti/
A Dtn40.c37 u64 cfg_base; in tn40_fifo_alloc() local
57 cfg_base = lower_32_bits((f->da & TN40_TX_RX_CFG0_BASE) | fsz_type); in tn40_fifo_alloc()
58 tn40_write_reg(priv, reg_cfg0, cfg_base); in tn40_fifo_alloc()
/drivers/net/usb/
A Dsmsc75xx.c1531 int cfg_base = WUF_CFGX + filter * 4; in smsc75xx_write_wuff() local
1535 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg); in smsc75xx_write_wuff()

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