| /drivers/gpio/ |
| A D | gpio-crystalcove.c | 120 if (cg->set_irq_mask) in crystalcove_update_irq_mask()
130 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value); in crystalcove_update_irq_ctrl()
219 mutex_lock(&cg->buslock); in crystalcove_bus_lock()
231 cg->update = 0; in crystalcove_bus_sync_unlock()
260 cg->set_irq_mask = true; in crystalcove_irq_mask()
343 cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL); in crystalcove_gpio_probe()
344 if (!cg) in crystalcove_gpio_probe()
353 cg->chip.base = -1; in crystalcove_gpio_probe()
356 cg->chip.parent = dev; in crystalcove_gpio_probe()
360 girq = &cg->chip.irq; in crystalcove_gpio_probe()
[all …]
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| /drivers/power/supply/ |
| A D | chagall-battery.c | 53 struct chagall_battery_data *cg = in chagall_led_set_brightness_amber() local
62 struct chagall_battery_data *cg = in chagall_led_set_brightness_white() local
173 if (cg->last_state != state) { in chagall_battery_poll_work()
174 cg->last_state = state; in chagall_battery_poll_work()
194 struct chagall_battery_data *cg; in chagall_battery_probe() local
199 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); in chagall_battery_probe()
200 if (!cg) in chagall_battery_probe()
203 cfg.drv_data = cg; in chagall_battery_probe()
206 i2c_set_clientdata(client, cg); in chagall_battery_probe()
209 if (IS_ERR(cg->regmap)) in chagall_battery_probe()
[all …]
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| A D | rk817_charger.c | 573 static irqreturn_t rk817_plug_in_isr(int irq, void *cg) in rk817_plug_in_isr() argument
577 charger = (struct rk817_charger *)cg; in rk817_plug_in_isr()
591 static irqreturn_t rk817_plug_out_isr(int irq, void *cg) in rk817_plug_out_isr() argument
596 charger = (struct rk817_charger *)cg; in rk817_plug_out_isr()
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| /drivers/clk/mediatek/ |
| A D | clk-gate.c | 36 regmap_read(cg->regmap, cg->sta_ofs, &val); in mtk_get_clockgating()
55 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); in mtk_cg_set_bit()
62 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); in mtk_cg_clr_bit()
69 regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); in mtk_cg_set_bit_no_setclr()
76 regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); in mtk_cg_clr_bit_no_setclr()
166 cg = kzalloc(sizeof(*cg), GFP_KERNEL); in mtk_clk_register_gate()
167 if (!cg) in mtk_clk_register_gate()
180 cg->bit = bit; in mtk_clk_register_gate()
186 kfree(cg); in mtk_clk_register_gate()
190 return &cg->hw; in mtk_clk_register_gate()
[all …]
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| /drivers/clk/ |
| A D | clk-qoriq.c | 477 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
509 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
524 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
529 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
536 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
546 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
551 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
552 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
958 hwc->cg = cg; in create_mux_common()
1047 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
[all …]
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| A D | clk-en7523.c | 398 void __iomem *np_base = cg->base; in en7523_pci_prepare()
437 void __iomem *np_base = cg->base; in en7523_pci_unprepare()
453 struct en_clk_gate *cg; in en7523_register_pcie_clk() local
455 cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL); in en7523_register_pcie_clk()
456 if (!cg) in en7523_register_pcie_clk()
459 cg->base = np_base; in en7523_register_pcie_clk()
460 cg->hw.init = &init; in en7523_register_pcie_clk()
463 init.ops->unprepare(&cg->hw); in en7523_register_pcie_clk()
468 return &cg->hw; in en7523_register_pcie_clk()
484 void __iomem *np_base = cg->base; in en7581_pci_enable()
[all …]
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| /drivers/clk/sunxi-ng/ |
| A D | ccu_gate.c | 33 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_disable() local
35 return ccu_gate_helper_disable(&cg->common, cg->enable); in ccu_gate_disable()
61 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_enable() local
63 return ccu_gate_helper_enable(&cg->common, cg->enable); in ccu_gate_enable()
77 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_is_enabled() local
79 return ccu_gate_helper_is_enabled(&cg->common, cg->enable); in ccu_gate_is_enabled()
85 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_recalc_rate() local
88 if (cg->common.features & CCU_FEATURE_ALL_PREDIV) in ccu_gate_recalc_rate()
89 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
97 struct ccu_gate *cg = hw_to_ccu_gate(hw); in ccu_gate_determine_rate() local
[all …]
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| /drivers/infiniband/core/ |
| A D | cgroup.c | 41 return rdmacg_try_charge(&cg_obj->cg, &device->cg_device, in ib_rdmacg_try_charge()
50 rdmacg_uncharge(cg_obj->cg, &device->cg_device, in ib_rdmacg_uncharge()
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| /drivers/clk/thead/ |
| A D | clk-th1520-ap.c | 1164 struct ccu_gate *cg = hw_to_ccu_gate(&plat_data->th1520_gate_clks[i]->hw); in th1520_clk_probe() local
1169 cg->common.hw.init->name, in th1520_clk_probe()
1170 cg->common.hw.init->parent_data, in th1520_clk_probe()
1171 cg->common.hw.init->flags, in th1520_clk_probe()
1172 base + cg->common.cfg0, in th1520_clk_probe()
1173 ffs(cg->enable) - 1, 0, NULL); in th1520_clk_probe()
1177 priv->hws[cg->common.clkid] = hw; in th1520_clk_probe()
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| /drivers/gpu/drm/xe/ |
| A D | xe_ttm_vram_mgr.c | 317 man->cg = drmm_cgroup_register_region(&xe->drm, name, size); in __xe_ttm_vram_mgr_init()
318 if (IS_ERR(man->cg)) in __xe_ttm_vram_mgr_init()
319 return PTR_ERR(man->cg); in __xe_ttm_vram_mgr_init()
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| /drivers/gpu/drm/ttm/ |
| A D | ttm_resource.c | 385 if (man->cg) { in ttm_resource_alloc()
386 ret = dmem_cgroup_try_charge(man->cg, bo->base.size, &pool, ret_limit_pool); in ttm_resource_alloc()
423 if (man->cg) in ttm_resource_free()
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_vram_mgr.c | 927 man->cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev->gmc.real_vram_size); in amdgpu_vram_mgr_init()
928 if (IS_ERR(man->cg)) in amdgpu_vram_mgr_init()
929 return PTR_ERR(man->cg); in amdgpu_vram_mgr_init()
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| /drivers/clk/tegra/ |
| A D | clk-dfll.c | 294 u32 cg; member
887 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
1407 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1913 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
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| /drivers/video/fbdev/ |
| A D | simplefb.c | 52 u32 cg = green >> (16 - info->var.green.length); in simplefb_setcolreg() local
60 (cg << info->var.green.offset) | in simplefb_setcolreg()
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| A D | offb.c | 107 u32 cg = green >> (16 - info->var.green.length); in offb_setcolreg() local
115 (cg << info->var.green.offset) | in offb_setcolreg()
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| /drivers/staging/media/ipu3/include/uapi/ |
| A D | intel-ipu3.h | 685 __u32 cg:5; member
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| /drivers/scsi/lpfc/ |
| A D | lpfc_sli.c | 1786 int wsigmax, wfpinmax, cg, tdp; in lpfc_cmf_sync_cmpl() local
1815 cg = bf_get(lpfc_wcqe_c_cmf_cg, wcqe); in lpfc_cmf_sync_cmpl()
1872 bwpcent, bw, pcent, s, cg, in lpfc_cmf_sync_cmpl()
1879 bwpcent, bw, pcent, s, cg, in lpfc_cmf_sync_cmpl()
1888 wsigmax, cg, phba->cmf_active_info); in lpfc_cmf_sync_cmpl()
1896 wfpinmax, cg, phba->cmf_active_info); in lpfc_cmf_sync_cmpl()
1901 bwpcent, bw, pcent, s, cg, in lpfc_cmf_sync_cmpl()
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