| /drivers/gpu/drm/amd/amdgpu/ |
| A D | umc_v8_7.c | 45 uint32_t ch_inst) in get_umc_v8_7_reg_offset() argument
103 umc_inst, ch_inst, in umc_v8_7_ecc_info_query_ras_error_count()
106 umc_inst, ch_inst, in umc_v8_7_ecc_info_query_ras_error_count()
132 uint32_t ch_inst, in umc_v8_7_ecc_info_query_error_address() argument
175 ch_inst, in umc_v8_7_ecc_info_query_ras_error_address()
227 ch_inst); in umc_v8_7_clear_error_count()
313 ch_inst); in umc_v8_7_query_ras_error_count()
329 uint32_t ch_inst, in umc_v8_7_query_error_address() argument
380 ch_inst); in umc_v8_7_query_ras_error_address()
385 ch_inst, in umc_v8_7_query_ras_error_address()
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| A D | umc_v6_7.c | 48 uint32_t ch_inst) in get_umc_v6_7_reg_offset() argument
55 ch_inst = index % 4; in get_umc_v6_7_reg_offset()
104 umc_inst, ch_inst); in umc_v6_7_ecc_info_query_correctable_error_count()
146 umc_inst, ch_inst); in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
165 uint32_t ch_inst, void *data) in umc_v6_7_ecc_info_querry_ecc_error_count() argument
170 umc_inst, ch_inst, in umc_v6_7_ecc_info_querry_ecc_error_count()
174 umc_inst, ch_inst, in umc_v6_7_ecc_info_querry_ecc_error_count()
248 ch_inst, umc_inst); in umc_v6_7_ecc_info_query_error_address()
264 uint32_t ch_inst, in umc_v6_7_query_correctable_error_count() argument
423 ch_inst, umc_inst); in umc_v6_7_query_ecc_error_count()
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| A D | umc_v8_10.c | 73 uint32_t ch_inst) in get_umc_v8_10_reg_offset() argument
81 uint32_t ch_inst, void *data) in umc_v8_10_clear_error_count_per_channel() argument
145 uint32_t ch_inst, void *data) in umc_v8_10_query_ecc_error_count() argument
219 ch_inst]; in umc_v8_10_convert_error_address()
246 uint32_t ch_inst, void *data) in umc_v8_10_query_error_address() argument
296 uint32_t ch_inst, void *data) in umc_v8_10_err_cnt_init_per_channel() argument
346 ch_inst; in umc_v8_10_ecc_info_query_correctable_error_count()
365 ch_inst; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
381 uint32_t ch_inst, void *data) in umc_v8_10_ecc_info_query_ecc_error_count() argument
386 node_inst, umc_inst, ch_inst, in umc_v8_10_ecc_info_query_ecc_error_count()
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| A D | umc_v6_1.c | 89 uint32_t ch_inst) in get_umc_6_reg_offset() argument
148 uint32_t ch_inst = 0; in umc_v6_1_clear_error_count() local
159 ch_inst); in umc_v6_1_clear_error_count()
260 uint32_t ch_inst = 0; in umc_v6_1_query_ras_error_count() local
275 ch_inst); in umc_v6_1_query_ras_error_count()
298 uint32_t ch_inst, in umc_v6_1_query_error_address() argument
359 uint32_t ch_inst = 0; in umc_v6_1_query_ras_error_address() local
374 ch_inst); in umc_v6_1_query_ras_error_address()
379 ch_inst, in umc_v6_1_query_ras_error_address()
432 uint32_t ch_inst = 0; in umc_v6_1_err_cnt_init() local
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| A D | amdgpu_umc.h | 46 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_i… argument
47 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst… argument
52 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \ argument
53 LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
94 uint32_t umc_inst, uint32_t ch_inst, void *data);
172 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst);
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| A D | umc_v8_14.c | 32 uint32_t ch_inst) in get_umc_v8_14_reg_offset() argument
34 return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst; in get_umc_v8_14_reg_offset()
39 uint32_t ch_inst, void *data) in umc_v8_14_clear_error_count_per_channel() argument
43 get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst); in umc_v8_14_clear_error_count_per_channel()
94 uint32_t ch_inst, void *data) in umc_v8_14_query_error_count_per_channel() argument
98 get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst); in umc_v8_14_query_error_count_per_channel()
121 uint32_t ch_inst, void *data) in umc_v8_14_err_cnt_init_per_channel() argument
126 get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst); in umc_v8_14_err_cnt_init_per_channel()
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| A D | amdgpu_umc.c | 33 uint32_t ch_inst, uint32_t umc_inst) in amdgpu_umc_convert_error_address() argument
38 err_data, err_addr, ch_inst, umc_inst); in amdgpu_umc_convert_error_address()
75 ch_inst, umc_inst); in amdgpu_umc_page_retirement_mca()
396 uint32_t ch_inst; in amdgpu_umc_loop_all_aid() local
412 LOOP_UMC_CH_INST(ch_inst) { in amdgpu_umc_loop_all_aid()
415 node_inst, umc_inst, ch_inst); in amdgpu_umc_loop_all_aid()
420 node_inst, umc_inst, ch_inst, ret); in amdgpu_umc_loop_all_aid()
434 uint32_t ch_inst = 0; in amdgpu_umc_loop_channels() local
445 node_inst, umc_inst, ch_inst, ret); in amdgpu_umc_loop_channels()
454 umc_inst, ch_inst, ret); in amdgpu_umc_loop_channels()
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| A D | umc_v12_0.c | 37 uint32_t ch_inst) in get_umc_v12_0_reg_offset() argument
39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v12_0_reg_offset()
43 ch_inst = index % 4; in get_umc_v12_0_reg_offset()
51 uint32_t ch_inst, void *data) in umc_v12_0_reset_error_count_per_channel() argument
55 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v12_0_reset_error_count_per_channel()
139 uint32_t ch_inst, void *data) in umc_v12_0_query_error_count() argument
152 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v12_0_query_error_count()
328 uint32_t ch_inst, void *data) in umc_v12_0_query_error_address() argument
336 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v12_0_query_error_address()
371 addr_in.ma.ch_inst = ch_inst; in umc_v12_0_query_error_address()
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| A D | umc_v6_7.h | 76 uint32_t ch_inst, uint32_t umc_inst);
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| A D | ta_ras_if.h | 162 uint32_t ch_inst; member
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| A D | amdgpu_ras.c | 2760 addr_in.ma.ch_inst = bps->mem_channel; in amdgpu_ras_mca2pa_by_idx()
2796 addr_in.ma.ch_inst = bps->mem_channel; in amdgpu_ras_mca2pa()
4615 uint32_t umc_inst = 0, ch_inst = 0; in amdgpu_bad_page_notifier() local
4649 ch_inst = GET_CHAN_INDEX(m->ipid); in amdgpu_bad_page_notifier()
4652 umc_inst, ch_inst); in amdgpu_bad_page_notifier()
4654 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst)) in amdgpu_bad_page_notifier()
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