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Searched refs:clear_surface_dcc_and_tiling (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/amd/display/dc/hwss/dce80/
A Ddce80_hwseq.c53 dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling; in dce80_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/core/
A Ddc_surface.c295 if (dc->hwss.clear_surface_dcc_and_tiling) in dc_plane_force_dcc_and_tiling_disable()
296 dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling); in dc_plane_force_dcc_and_tiling_disable()
/drivers/gpu/drm/amd/display/dc/hwss/dce100/
A Ddce100_hwseq.c141 dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling; in dce100_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_init.c43 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_init.c39 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_init.c39 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn301/
A Ddcn301_init.c42 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn21/
A Ddcn21_init.c40 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dce120/
A Ddce120_hwseq.c268 dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling; in dce120_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_init.c40 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_init.c45 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
A Ddcn31_init.c43 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn351/
A Ddcn351_init.c46 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_init.c21 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_init.c42 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_init.c47 .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
/drivers/gpu/drm/amd/display/dc/hwss/dce60/
A Ddce60_hwseq.c431 dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling; in dce60_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/hwss/
A Dhw_sequencer.h248 …void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state… member
/drivers/gpu/drm/amd/display/dc/hwss/dce110/
A Ddce110_hwseq.c3366 .clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling,

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