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Searched refs:clk1 (Results 1 – 21 of 21) sorted by relevance

/drivers/clk/spear/
A Dspear1340_clock.c441 struct clk *clk, *clk1; in spear1340_clk_init() local
474 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear1340_clk_init()
476 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear1340_clk_init()
487 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear1340_clk_init()
498 clk_register_clkdev(clk1, "pll3_clk", NULL); in spear1340_clk_init()
504 clk_register_clkdev(clk1, "pll4_clk", NULL); in spear1340_clk_init()
677 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1340_clk_init()
689 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1340_clk_init()
715 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); in spear1340_clk_init()
778 &clk1); in spear1340_clk_init()
[all …]
A Dspear3xx_clock.c390 struct clk *clk, *clk1, *ras_apb_clk; in spear3xx_clk_init() local
414 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear3xx_clk_init()
416 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear3xx_clk_init()
420 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear3xx_clk_init()
422 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear3xx_clk_init()
436 &_lock, &clk1); in spear3xx_clk_init()
454 &_lock, &clk1); in spear3xx_clk_init()
506 &_lock, &clk1); in spear3xx_clk_init()
512 &_lock, &clk1); in spear3xx_clk_init()
524 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear3xx_clk_init()
[all …]
A Dspear6xx_clock.c116 struct clk *clk, *clk1; in spear6xx_clk_init() local
136 &_lock, &clk1, NULL); in spear6xx_clk_init()
138 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear6xx_clk_init()
142 &_lock, &clk1, NULL); in spear6xx_clk_init()
144 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear6xx_clk_init()
162 &_lock, &clk1); in spear6xx_clk_init()
164 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); in spear6xx_clk_init()
182 &_lock, &clk1); in spear6xx_clk_init()
184 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); in spear6xx_clk_init()
198 &_lock, &clk1); in spear6xx_clk_init()
[all …]
A Dspear1310_clock.c384 struct clk *clk, *clk1; in spear1310_clk_init() local
419 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear1310_clk_init()
430 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear1310_clk_init()
441 clk_register_clkdev(clk1, "pll3_clk", NULL); in spear1310_clk_init()
447 clk_register_clkdev(clk1, "pll4_clk", NULL); in spear1310_clk_init()
552 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1310_clk_init()
581 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1310_clk_init()
593 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1310_clk_init()
619 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); in spear1310_clk_init()
681 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); in spear1310_clk_init()
[all …]
/drivers/clk/ti/
A Dclk-33xx.c272 struct clk *clk1, *clk2; in am33xx_dt_clk_init() local
292 clk1 = clk_get_sys(NULL, "sys_clkin_ck"); in am33xx_dt_clk_init()
294 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
297 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
305 clk1 = clk_get_sys(NULL, "wdt1_fck"); in am33xx_dt_clk_init()
307 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
A Dclk-43xx.c275 struct clk *clk1, *clk2; in am43xx_dt_clk_init() local
296 clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); in am43xx_dt_clk_init()
298 clk_set_parent(clk1, clk2); in am43xx_dt_clk_init()
A Dadpll.c267 struct clk *clk1, in ti_adpll_init_mux() argument
279 parents[1] = __clk_get_name(clk1); in ti_adpll_init_mux()
576 struct clk *clk1) in ti_adpll_init_clkout() argument
607 parent_names[1] = __clk_get_name(clk1); in ti_adpll_init_clkout()
/drivers/clocksource/
A Dtimer-sp804.c259 struct clk *clk1, *clk2; in sp804_of_init() local
278 clk1 = of_clk_get(np, 0); in sp804_of_init()
279 if (IS_ERR(clk1)) in sp804_of_init()
280 clk1 = NULL; in sp804_of_init()
291 clk2 = clk1; in sp804_of_init()
307 name, clk1, 1); in sp804_of_init()
312 ret = sp804_clockevents_init(timer1_base, irq, clk1, name); in sp804_of_init()
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dgf100.c279 u32 clk0, clk1 = 0; in calc_clk() local
292 clk1 = calc_pll(clk, idx, freq, &info->coef); in calc_clk()
294 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
295 clk1 = calc_div(clk, idx, clk1, freq, &div1P); in calc_clk()
299 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk()
318 info->freq = clk1; in calc_clk()
A Dgk104.c293 u32 clk0, clk1 = 0; in calc_clk() local
306 clk1 = calc_pll(clk, idx, freq, &info->coef); in calc_clk()
308 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
309 clk1 = calc_div(clk, idx, clk1, freq, &div1P); in calc_clk()
313 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk()
332 info->freq = clk1; in calc_clk()
A Dmcp77.c184 u32 clk0 = src, clk1 = src; in calc_P() local
187 clk1 = clk0 << (*div ? 1 : 0); in calc_P()
193 if (target - clk0 <= clk1 - target) in calc_P()
196 return clk1; in calc_P()
A Dnv50.c347 u32 clk0 = src, clk1 = src; in calc_div() local
350 clk1 = clk0 << (*div ? 1 : 0); in calc_div()
356 if (target - clk0 <= clk1 - target) in calc_div()
359 return clk1; in calc_div()
/drivers/clk/rockchip/
A Dclk-rk3188.c823 struct clk *clk1, *clk2; in rk3188a_clk_init() local
844 clk1 = __clk_lookup("aclk_cpu_pre"); in rk3188a_clk_init()
846 if (clk1 && clk2) { in rk3188a_clk_init()
847 rate = clk_get_rate(clk1); in rk3188a_clk_init()
849 ret = clk_set_parent(clk1, clk2); in rk3188a_clk_init()
854 clk_set_rate(clk1, rate); in rk3188a_clk_init()
/drivers/clk/renesas/
A Drzv2h-cpg.c225 unsigned int clk1, clk2; in rzv2h_cpg_pll_clk_recalc_rate() local
231 clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset)); in rzv2h_cpg_pll_clk_recalc_rate()
234 rate = mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) + in rzv2h_cpg_pll_clk_recalc_rate()
235 CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2)); in rzv2h_cpg_pll_clk_recalc_rate()
237 return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1)); in rzv2h_cpg_pll_clk_recalc_rate()
A Dr9a08g045-cpg.c54 #define G3S_PLL146_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting)) argument
/drivers/clk/zynq/
A Dclkc.c175 enum zynq_clk clk1, const char *clk_name0, in zynq_clk_register_periph_clk() argument
200 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
211 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
/drivers/phy/cadence/
A Dphy-cadence-torrent.c364 struct clk *clk1; member
2816 if (IS_ERR(cdns_phy->clk1)) in cdns_torrent_of_get_clk()
2817 return dev_err_probe(cdns_phy->dev, PTR_ERR(cdns_phy->clk1), in cdns_torrent_of_get_clk()
2861 if (cdns_phy->clk1) { in cdns_torrent_clk()
2862 ret = clk_prepare_enable(cdns_phy->clk1); in cdns_torrent_clk()
2868 ref_clk1_rate = clk_get_rate(cdns_phy->clk1); in cdns_torrent_clk()
2900 clk_disable_unprepare(cdns_phy->clk1); in cdns_torrent_clk()
3159 clk_disable_unprepare(cdns_phy->clk1); in cdns_torrent_phy_probe()
3178 clk_disable_unprepare(cdns_phy->clk1); in cdns_torrent_phy_remove()
3342 clk_disable_unprepare(cdns_phy->clk1); in cdns_torrent_phy_suspend_noirq()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_6_ppt.c1309 uint32_t clk1, clk2; in smu_v13_0_6_print_clks() local
1333 clk1 = clocks.data[i].clocks_in_khz / 1000; in smu_v13_0_6_print_clks()
1338 if (curr_clk == clk1) { in smu_v13_0_6_print_clks()
1340 } else if (curr_clk >= clk1 && curr_clk < clk2) { in smu_v13_0_6_print_clks()
1341 level = (curr_clk - clk1) <= (clk2 - curr_clk) ? in smu_v13_0_6_print_clks()
1347 clk1, (level == i) ? "*" : ""); in smu_v13_0_6_print_clks()
/drivers/clk/
A Dclk_test.c3090 struct clk_dummy_context clk1; member
3176 clk_assigned_rates_register_clk(test, &ctx->clk1, np, in clk_assigned_rates_test_init()
3183 data->hws[1] = &ctx->clk1.hw; in clk_assigned_rates_test_init()
3213 KUNIT_EXPECT_EQ(test, ctx->clk1.rate, ASSIGNED_RATES_1_RATE); in clk_assigned_rates_assigns_multiple()
/drivers/pinctrl/
A Dpinctrl-lpc18xx.c417 LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
626 LPC18XX_PIN(clk1, PIN_CLK1),
/drivers/clk/qcom/
A Dclk-rpmh.c376 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);

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