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Searched refs:clk_ctrl (Results 1 – 25 of 39) sorted by relevance

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/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_1_7_msm8996.h69 .clk_ctrl = DPU_CLK_CTRL_VIG0,
77 .clk_ctrl = DPU_CLK_CTRL_VIG1,
85 .clk_ctrl = DPU_CLK_CTRL_VIG2,
93 .clk_ctrl = DPU_CLK_CTRL_VIG3,
101 .clk_ctrl = DPU_CLK_CTRL_RGB0,
109 .clk_ctrl = DPU_CLK_CTRL_RGB1,
117 .clk_ctrl = DPU_CLK_CTRL_RGB2,
125 .clk_ctrl = DPU_CLK_CTRL_RGB3,
133 .clk_ctrl = DPU_CLK_CTRL_DMA0,
141 .clk_ctrl = DPU_CLK_CTRL_DMA1,
A Ddpu_5_0_sm8150.h75 .clk_ctrl = DPU_CLK_CTRL_VIG0,
83 .clk_ctrl = DPU_CLK_CTRL_VIG1,
91 .clk_ctrl = DPU_CLK_CTRL_VIG2,
99 .clk_ctrl = DPU_CLK_CTRL_VIG3,
107 .clk_ctrl = DPU_CLK_CTRL_DMA0,
115 .clk_ctrl = DPU_CLK_CTRL_DMA1,
123 .clk_ctrl = DPU_CLK_CTRL_DMA2,
131 .clk_ctrl = DPU_CLK_CTRL_DMA3,
281 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_6_0_sm8250.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
318 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_7_0_sm8350.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
291 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_3_0_msm8998.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
A Ddpu_4_0_sdm845.h72 .clk_ctrl = DPU_CLK_CTRL_VIG0,
80 .clk_ctrl = DPU_CLK_CTRL_VIG1,
88 .clk_ctrl = DPU_CLK_CTRL_VIG2,
96 .clk_ctrl = DPU_CLK_CTRL_VIG3,
104 .clk_ctrl = DPU_CLK_CTRL_DMA0,
112 .clk_ctrl = DPU_CLK_CTRL_DMA1,
120 .clk_ctrl = DPU_CLK_CTRL_DMA2,
128 .clk_ctrl = DPU_CLK_CTRL_DMA3,
A Ddpu_8_1_sm8450.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
304 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_5_1_sc8180x.h75 .clk_ctrl = DPU_CLK_CTRL_VIG0,
83 .clk_ctrl = DPU_CLK_CTRL_VIG1,
91 .clk_ctrl = DPU_CLK_CTRL_VIG2,
99 .clk_ctrl = DPU_CLK_CTRL_VIG3,
107 .clk_ctrl = DPU_CLK_CTRL_DMA0,
115 .clk_ctrl = DPU_CLK_CTRL_DMA1,
123 .clk_ctrl = DPU_CLK_CTRL_DMA2,
131 .clk_ctrl = DPU_CLK_CTRL_DMA3,
287 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_4_1_sdm670.h31 .clk_ctrl = DPU_CLK_CTRL_VIG0,
39 .clk_ctrl = DPU_CLK_CTRL_VIG0,
47 .clk_ctrl = DPU_CLK_CTRL_DMA0,
55 .clk_ctrl = DPU_CLK_CTRL_DMA1,
63 .clk_ctrl = DPU_CLK_CTRL_DMA2,
A Ddpu_5_3_sm6150.h69 .clk_ctrl = DPU_CLK_CTRL_VIG0,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
85 .clk_ctrl = DPU_CLK_CTRL_DMA1,
93 .clk_ctrl = DPU_CLK_CTRL_DMA2,
101 .clk_ctrl = DPU_CLK_CTRL_DMA3,
159 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_8_4_sa8775p.h73 .clk_ctrl = DPU_CLK_CTRL_VIG0,
81 .clk_ctrl = DPU_CLK_CTRL_VIG1,
89 .clk_ctrl = DPU_CLK_CTRL_VIG2,
97 .clk_ctrl = DPU_CLK_CTRL_VIG3,
105 .clk_ctrl = DPU_CLK_CTRL_DMA0,
113 .clk_ctrl = DPU_CLK_CTRL_DMA1,
121 .clk_ctrl = DPU_CLK_CTRL_DMA2,
129 .clk_ctrl = DPU_CLK_CTRL_DMA3,
311 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_8_0_sc8280xp.h73 .clk_ctrl = DPU_CLK_CTRL_VIG0,
81 .clk_ctrl = DPU_CLK_CTRL_VIG1,
89 .clk_ctrl = DPU_CLK_CTRL_VIG2,
97 .clk_ctrl = DPU_CLK_CTRL_VIG3,
105 .clk_ctrl = DPU_CLK_CTRL_DMA0,
113 .clk_ctrl = DPU_CLK_CTRL_DMA1,
121 .clk_ctrl = DPU_CLK_CTRL_DMA2,
129 .clk_ctrl = DPU_CLK_CTRL_DMA3,
A Ddpu_6_2_sc7180.h55 .clk_ctrl = DPU_CLK_CTRL_VIG0,
63 .clk_ctrl = DPU_CLK_CTRL_DMA0,
71 .clk_ctrl = DPU_CLK_CTRL_DMA1,
79 .clk_ctrl = DPU_CLK_CTRL_DMA2,
154 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_6_4_sm6350.h62 .clk_ctrl = DPU_CLK_CTRL_VIG0,
70 .clk_ctrl = DPU_CLK_CTRL_DMA0,
78 .clk_ctrl = DPU_CLK_CTRL_DMA1,
86 .clk_ctrl = DPU_CLK_CTRL_DMA2,
148 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_5_2_sm7150.h72 .clk_ctrl = DPU_CLK_CTRL_VIG0,
80 .clk_ctrl = DPU_CLK_CTRL_VIG1,
88 .clk_ctrl = DPU_CLK_CTRL_DMA0,
96 .clk_ctrl = DPU_CLK_CTRL_DMA1,
104 .clk_ctrl = DPU_CLK_CTRL_DMA2,
247 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_7_2_sc7280.h59 .clk_ctrl = DPU_CLK_CTRL_VIG0,
67 .clk_ctrl = DPU_CLK_CTRL_DMA0,
75 .clk_ctrl = DPU_CLK_CTRL_DMA1,
83 .clk_ctrl = DPU_CLK_CTRL_DMA2,
165 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_1_15_msm8917.h53 .clk_ctrl = DPU_CLK_CTRL_VIG0,
61 .clk_ctrl = DPU_CLK_CTRL_RGB0,
69 .clk_ctrl = DPU_CLK_CTRL_RGB1,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
A Ddpu_1_14_msm8937.h53 .clk_ctrl = DPU_CLK_CTRL_VIG0,
61 .clk_ctrl = DPU_CLK_CTRL_RGB0,
69 .clk_ctrl = DPU_CLK_CTRL_RGB1,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
A Ddpu_3_2_sdm660.h69 .clk_ctrl = DPU_CLK_CTRL_VIG0,
77 .clk_ctrl = DPU_CLK_CTRL_VIG1,
85 .clk_ctrl = DPU_CLK_CTRL_DMA0,
93 .clk_ctrl = DPU_CLK_CTRL_DMA1,
101 .clk_ctrl = DPU_CLK_CTRL_DMA2,
A Ddpu_1_16_msm8953.h53 .clk_ctrl = DPU_CLK_CTRL_VIG0,
61 .clk_ctrl = DPU_CLK_CTRL_RGB0,
69 .clk_ctrl = DPU_CLK_CTRL_RGB1,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
A Ddpu_5_4_sm6125.h69 .clk_ctrl = DPU_CLK_CTRL_VIG0,
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
85 .clk_ctrl = DPU_CLK_CTRL_DMA1,
138 .clk_ctrl = DPU_CLK_CTRL_WB2,
A Ddpu_3_3_sdm630.h68 .clk_ctrl = DPU_CLK_CTRL_VIG0,
76 .clk_ctrl = DPU_CLK_CTRL_DMA0,
84 .clk_ctrl = DPU_CLK_CTRL_DMA1,
92 .clk_ctrl = DPU_CLK_CTRL_DMA2,
/drivers/net/wireless/st/cw1200/
A Dcw1200_sdio.c194 if (pdata->clk_ctrl) in cw1200_sdio_off()
195 pdata->clk_ctrl(pdata, false); in cw1200_sdio_off()
228 if (pdata->clk_ctrl) { in cw1200_sdio_on()
229 if (pdata->clk_ctrl(pdata, true)) { in cw1200_sdio_on()
A Dcw1200_spi.c290 if (pdata->clk_ctrl) in cw1200_spi_off()
291 pdata->clk_ctrl(pdata, false); in cw1200_spi_off()
313 if (pdata->clk_ctrl) { in cw1200_spi_on()
314 if (pdata->clk_ctrl(pdata, true)) { in cw1200_spi_on()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_top.c71 enum dpu_clk_ctrl_type clk_ctrl, bool enable) in dpu_hw_setup_clk_force_ctrl() argument
76 if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX) in dpu_hw_setup_clk_force_ctrl()
79 return dpu_hw_clk_force_ctrl(&mdp->hw, &mdp->caps->clk_ctrls[clk_ctrl], enable); in dpu_hw_setup_clk_force_ctrl()

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