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Searched refs:clk_ctrls (Results 1 – 25 of 32) sorted by relevance

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/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_6_5_qcm2290.h22 .clk_ctrls = {
A Ddpu_6_3_sm6115.h22 .clk_ctrls = {
A Ddpu_6_9_sm6375.h23 .clk_ctrls = {
A Ddpu_4_1_sdm670.h14 .clk_ctrls = {
A Ddpu_1_15_msm8917.h22 .clk_ctrls = {
A Ddpu_1_14_msm8937.h22 .clk_ctrls = {
A Ddpu_1_16_msm8953.h22 .clk_ctrls = {
A Ddpu_5_4_sm6125.h25 .clk_ctrls = {
A Ddpu_6_2_sc7180.h22 .clk_ctrls = {
A Ddpu_3_3_sdm630.h25 .clk_ctrls = {
A Ddpu_6_4_sm6350.h24 .clk_ctrls = {
A Ddpu_5_3_sm6150.h23 .clk_ctrls = {
A Ddpu_7_2_sc7280.h22 .clk_ctrls = {
A Ddpu_3_2_sdm660.h25 .clk_ctrls = {
A Ddpu_1_7_msm8996.h25 .clk_ctrls = {
A Ddpu_3_0_msm8998.h26 .clk_ctrls = {
A Ddpu_5_2_sm7150.h26 .clk_ctrls = {
A Ddpu_4_0_sdm845.h26 .clk_ctrls = {
A Ddpu_5_0_sm8150.h26 .clk_ctrls = {
A Ddpu_6_0_sm8250.h24 .clk_ctrls = {
A Ddpu_7_0_sm8350.h24 .clk_ctrls = {
A Ddpu_9_0_sm8550.h24 .clk_ctrls = {
A Ddpu_9_1_sar2130p.h24 .clk_ctrls = {
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_catalog.h381 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; member
A Ddpu_hw_top.c79 return dpu_hw_clk_force_ctrl(&mdp->hw, &mdp->caps->clk_ctrls[clk_ctrl], enable); in dpu_hw_setup_clk_force_ctrl()

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