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Searched refs:clk_div (Results 1 – 25 of 71) sorted by relevance

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/drivers/pwm/
A Dpwm-crc.c42 int clk_div; in crc_pwm_calc_clk_div() local
44 clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); in crc_pwm_calc_clk_div()
46 if (clk_div > 0) in crc_pwm_calc_clk_div()
47 clk_div--; in crc_pwm_calc_clk_div()
49 return clk_div; in crc_pwm_calc_clk_div()
100 int clk_div = crc_pwm_calc_clk_div(state->period); in crc_pwm_apply() local
104 clk_div | pwm_output_enable); in crc_pwm_apply()
127 unsigned int clk_div, clk_div_reg, duty_cycle_reg; in crc_pwm_get_state() local
142 clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; in crc_pwm_get_state()
145 DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ); in crc_pwm_get_state()
A Dpwm-mtk-disp.c73 u32 clk_div, period, high_width, value; in mtk_disp_pwm_apply() local
118 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
120 if (clk_div > PWM_CLKDIV_MAX) { in mtk_disp_pwm_apply()
128 div = NSEC_PER_SEC * (clk_div + 1); in mtk_disp_pwm_apply()
151 clk_div << PWM_CLKDIV_SHIFT); in mtk_disp_pwm_apply()
178 u32 clk_div, pwm_en, con0, con1; in mtk_disp_pwm_get_state() local
209 clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0); in mtk_disp_pwm_get_state()
215 state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); in mtk_disp_pwm_get_state()
217 state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC, in mtk_disp_pwm_get_state()
/drivers/net/ethernet/xilinx/
A Dll_temac_mdio.c70 int clk_div; in temac_mdio_setup() local
82 clk_div = 0x3f; /* worst-case default setting */ in temac_mdio_setup()
84 clk_div = bus_hz / (2500 * 1000 * 2) - 1; in temac_mdio_setup()
85 if (clk_div < 1) in temac_mdio_setup()
86 clk_div = 1; in temac_mdio_setup()
87 if (clk_div > 0x3f) in temac_mdio_setup()
88 clk_div = 0x3f; in temac_mdio_setup()
94 temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div); in temac_mdio_setup()
A Dxilinx_axienet_mdio.c179 u32 clk_div; in axienet_mdio_enable() local
240 clk_div = (host_clock / (mdio_freq * 2)) - 1; in axienet_mdio_enable()
247 clk_div++; in axienet_mdio_enable()
250 if (clk_div & ~XAE_MDIO_MC_CLOCK_DIVIDE_MAX) { in axienet_mdio_enable()
254 lp->mii_clk_div = (u8)clk_div; in axienet_mdio_enable()
/drivers/mfd/
A Dfsl-imx25-tsadc.c102 unsigned clk_div; in mx25_tsadc_setup_clk() local
114 clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000); in mx25_tsadc_setup_clk()
115 dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div); in mx25_tsadc_setup_clk()
118 clk_div -= 2; in mx25_tsadc_setup_clk()
119 clk_div /= 2; in mx25_tsadc_setup_clk()
125 clk_div = max_t(unsigned, 4, clk_div); in mx25_tsadc_setup_clk()
128 clk_get_rate(tsadc->clk) / (2 * clk_div + 2)); in mx25_tsadc_setup_clk()
132 MX25_TGCR_ADCCLKCFG(clk_div)); in mx25_tsadc_setup_clk()
/drivers/clk/mxs/
A Dclk-div.c21 struct clk_div { struct
28 static inline struct clk_div *to_clk_div(struct clk_hw *hw) in to_clk_div() argument
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div()
/drivers/i2c/busses/
A Di2c-sun6i-p2wi.c192 int clk_div; in p2wi_probe() local
286 clk_div = parent_clk_freq / clk_freq; in p2wi_probe()
287 if (!clk_div) { in p2wi_probe()
291 clk_div = 1; in p2wi_probe()
292 } else if (clk_div > P2WI_CCR_MAX_CLK_DIV) { in p2wi_probe()
296 clk_div = P2WI_CCR_MAX_CLK_DIV; in p2wi_probe()
299 writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div), in p2wi_probe()
A Di2c-mt7621.c65 u32 clk_div; member
96 iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN | in mtk_i2c_reset()
259 i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1; in mtk_i2c_init()
260 if (i2c->clk_div < 99) in mtk_i2c_init()
261 i2c->clk_div = 99; in mtk_i2c_init()
262 if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX) in mtk_i2c_init()
263 i2c->clk_div = SM0CTL0_CLK_DIV_MAX; in mtk_i2c_init()
A Di2c-pasemi-platform.c32 data->smbus.clk_div = DIV_ROUND_UP(clk_rate, 16 * frequency); in pasemi_platform_i2c_calc_clk_div()
33 if (data->smbus.clk_div < 4) in pasemi_platform_i2c_calc_clk_div()
37 if (data->smbus.clk_div > 0xff) in pasemi_platform_i2c_calc_clk_div()
/drivers/spi/
A Dspi-hisi-kunpeng.c117 u16 clk_div; /* baud rate divider */ member
280 if (chip->clk_div % chip->div_pre == 0) in __hisi_calc_div_reg()
286 if (chip->div_pre > chip->clk_div) in __hisi_calc_div_reg()
287 chip->div_pre = chip->clk_div; in __hisi_calc_div_reg()
289 chip->div_post = (chip->clk_div / chip->div_pre) - 1; in __hisi_calc_div_reg()
298 chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1; in hisi_calc_effective_speed()
299 chip->clk_div &= 0xfffe; in hisi_calc_effective_speed()
300 if (chip->clk_div > CLK_DIV_MAX) in hisi_calc_effective_speed()
301 chip->clk_div = CLK_DIV_MAX; in hisi_calc_effective_speed()
303 effective_speed = host->max_speed_hz / chip->clk_div; in hisi_calc_effective_speed()
A Dspi-s3c64xx.c172 int clk_div; member
1516 .clk_div = 2,
1526 .clk_div = 2,
1535 .clk_div = 2,
1545 .clk_div = 2,
1557 .clk_div = 2,
1569 .clk_div = 2,
1581 .clk_div = 4,
1595 .clk_div = 4,
1609 .clk_div = 2,
[all …]
A Dspi-axi-spi-engine.c270 unsigned int clk_div, max_hz = msg->spi->controller->max_speed_hz; in spi_engine_precompile_message() local
280 clk_div = DIV_ROUND_UP(max_hz, xfer->speed_hz); in spi_engine_precompile_message()
281 xfer->effective_speed_hz = max_hz / min(clk_div, 256U); in spi_engine_precompile_message()
312 int clk_div, new_clk_div, inst_ns; in spi_engine_compile_message() local
322 clk_div = 1; in spi_engine_compile_message()
348 if (new_clk_div != clk_div) { in spi_engine_compile_message()
349 clk_div = new_clk_div; in spi_engine_compile_message()
353 clk_div - 1)); in spi_engine_compile_message()
394 if (clk_div != 1) in spi_engine_compile_message()
A Dspi-pxa2xx.c293 u32 clk_div, u8 bits) in pxa2xx_configure_sscr0() argument
297 return clk_div in pxa2xx_configure_sscr0()
301 return clk_div in pxa2xx_configure_sscr0()
910 unsigned int clk_div; in pxa2xx_ssp_get_clk_div() local
914 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); in pxa2xx_ssp_get_clk_div()
917 clk_div = ssp_get_clk_div(drv_data, rate); in pxa2xx_ssp_get_clk_div()
920 return clk_div << 8; in pxa2xx_ssp_get_clk_div()
942 u32 clk_div; in pxa2xx_spi_transfer_one() local
972 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); in pxa2xx_spi_transfer_one()
1013 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); in pxa2xx_spi_transfer_one()
/drivers/clk/
A Dclk-versaclock3.c902 &clk_div[VC3_DIV5].hw,
903 &clk_div[VC3_DIV4].hw
917 &clk_div[VC3_DIV5].hw,
918 &clk_div[VC3_DIV4].hw
933 &clk_div[VC3_DIV2].hw,
934 &clk_div[VC3_DIV4].hw
949 &clk_div[VC3_DIV1].hw,
950 &clk_div[VC3_DIV3].hw
965 &clk_div[VC3_DIV1].hw,
966 &clk_div[VC3_DIV3].hw
[all …]
/drivers/bus/
A Dsunxi-rsb.c655 int clk_div, ret; in sunxi_rsb_hw_init() local
682 clk_div = p_clk_freq / rsb->clk_freq / 2; in sunxi_rsb_hw_init()
683 if (!clk_div) in sunxi_rsb_hw_init()
684 clk_div = 1; in sunxi_rsb_hw_init()
685 else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1) in sunxi_rsb_hw_init()
686 clk_div = RSB_CCR_MAX_CLK_DIV + 1; in sunxi_rsb_hw_init()
688 clk_delay = clk_div >> 1; in sunxi_rsb_hw_init()
692 dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2); in sunxi_rsb_hw_init()
693 writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1), in sunxi_rsb_hw_init()
/drivers/media/i2c/
A Drj54n1cb0c.c157 struct rj54n1_clock_div clk_div; member
417 static const struct rj54n1_clock_div clk_div = { variable
839 rj54n1->clk_div.ratio_tg); in rj54n1_set_clock()
842 rj54n1->clk_div.ratio_t); in rj54n1_set_clock()
845 rj54n1->clk_div.ratio_r); in rj54n1_set_clock()
858 rj54n1->clk_div.ratio_op); in rj54n1_set_clock()
861 rj54n1->clk_div.ratio_o); in rj54n1_set_clock()
1336 rj54n1->clk_div = clk_div; in rj54n1_probe()
1346 (clk_div.ratio_tg + 1) / (clk_div.ratio_t + 1); in rj54n1_probe()
/drivers/media/dvb-frontends/
A Dstv6110.c29 u8 clk_div; member
214 priv->regs[RSTV6110_CTRL2] |= (priv->clk_div << 6); in stv6110_init()
398 reg0[2] |= (config->clk_div << 6); in stv6110_attach()
418 priv->clk_div = config->clk_div; in stv6110_attach()
/drivers/rtc/
A Drtc-s32g.c70 u32 clk_div; member
75 .clk_div = DIV512_32,
204 switch (priv->rtc_data->clk_div) { in rtc_clk_src_setup()
314 priv->rtc_hz = DIV_ROUND_UP(rtc_hz, priv->rtc_data->clk_div); in s32g_rtc_probe()
/drivers/gpu/drm/renesas/shmobile/
A Dshmob_drm_crtc.c205 unsigned int clk_div = sdev->config.clk_div; in shmob_drm_crtc_atomic_enable() local
227 if (clk_div) { in shmob_drm_crtc_atomic_enable()
232 lcdc_write(sdev, LDDCKPAT2R, (1 << (clk_div / 2)) - 1); in shmob_drm_crtc_atomic_enable()
234 if (clk_div == 1) in shmob_drm_crtc_atomic_enable()
237 value |= clk_div; in shmob_drm_crtc_atomic_enable()
A Dshmob_drm_drv.c213 sdev->config.clk_div = pdata->iface.clk_div; in shmob_drm_probe()
273 .clk_div = 5,
/drivers/video/fbdev/omap/
A Dsossi.c60 int clk_div; member
124 int div = t->clk_div; in calc_rd_timings()
175 int div = t->clk_div; in calc_wr_timings()
258 _set_timing(sossi.clk_div, in set_timing()
317 int div = t->clk_div; in sossi_convert_timings()
348 sossi.clk_div = t->tim[4]; in sossi_set_timings()
/drivers/leds/
A Dleds-bcm6358.c153 u32 clk_div; in bcm6358_leds_probe() local
169 of_property_read_u32(np, "brcm,clk-div", &clk_div); in bcm6358_leds_probe()
170 switch (clk_div) { in bcm6358_leds_probe()
/drivers/mmc/host/
A Dtifm_sd.c98 unsigned int clk_div; member
595 ((1000000000UL / host->clk_freq) * host->clk_div); in tifm_sd_set_data_timeout()
827 host->clk_div = clk_div1; in tifm_sd_ios()
833 host->clk_div = clk_div2; in tifm_sd_ios()
839 host->clk_div = 0; in tifm_sd_ios()
841 host->clk_div &= TIFM_MMCSD_CLKMASK; in tifm_sd_ios()
842 writel(host->clk_div in tifm_sd_ios()
883 host->clk_div = 61; in tifm_sd_initialize_host()
886 writel(host->clk_div | TIFM_MMCSD_POWER, in tifm_sd_initialize_host()
905 writel(host->clk_div | TIFM_MMCSD_POWER, in tifm_sd_initialize_host()
/drivers/usb/serial/
A Dch341.c181 unsigned int fact, div, clk_div; in ch341_get_divisor() local
205 clk_div = CH341_CLK_DIV(ps, fact); in ch341_get_divisor()
206 div = CH341_CLKRATE / (clk_div * speed); in ch341_get_divisor()
215 clk_div *= 2; in ch341_get_divisor()
226 if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >= in ch341_get_divisor()
227 16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) in ch341_get_divisor()
/drivers/mtd/devices/
A Dst_spi_fsm.c1899 uint32_t clk_div; in stfsm_set_freq() local
1907 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq); in stfsm_set_freq()
1908 if (clk_div < 2) in stfsm_set_freq()
1909 clk_div = 2; in stfsm_set_freq()
1910 else if (clk_div > 128) in stfsm_set_freq()
1911 clk_div = 128; in stfsm_set_freq()
1919 if (clk_div <= 4) in stfsm_set_freq()
1921 else if (clk_div <= 10) in stfsm_set_freq()
1924 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10); in stfsm_set_freq()
1927 emi_freq, spi_freq, clk_div); in stfsm_set_freq()
[all …]

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