| /drivers/clk/ |
| A D | clk-divider.c | 548 unsigned long clk_divider_flags, in __clk_hw_register_divider() argument
556 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { in __clk_hw_register_divider()
569 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) in __clk_hw_register_divider()
586 div->flags = clk_divider_flags; in __clk_hw_register_divider()
620 unsigned long clk_divider_flags, in clk_register_divider_table() argument
626 NULL, flags, reg, shift, width, clk_divider_flags, in clk_register_divider_table()
675 unsigned long clk_divider_flags, in __devm_clk_hw_register_divider() argument
686 clk_divider_flags, table, lock); in __devm_clk_hw_register_divider()
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| A D | clk-fractional-divider.c | 264 u8 clk_divider_flags, spinlock_t *lock) in clk_hw_register_fractional_divider() argument
286 fd->flags = clk_divider_flags; in clk_hw_register_fractional_divider()
304 u8 clk_divider_flags, spinlock_t *lock) in clk_register_fractional_divider() argument
309 reg, mshift, mwidth, nshift, nwidth, clk_divider_flags, in clk_register_fractional_divider()
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| A D | clk-npcm8xx.c | 72 unsigned long clk_divider_flags; member
380 div_data->clk_divider_flags, in npcm8xx_clk_probe()
400 div_data->clk_divider_flags, in npcm8xx_clk_probe()
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| A D | clk-npcm7xx.c | 155 u8 clk_divider_flags; member
493 div_data->clk_divider_flags, &npcm7xx_clk_lock); in npcm7xx_clk_init()
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| A D | clk-milbeaut.c | 460 u8 clk_divider_flags, const struct clk_div_table *table, in m10v_clk_hw_register_divider() argument
481 div->flags = clk_divider_flags; in m10v_clk_hw_register_divider()
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| A D | clk-stm32f4.c | 805 u8 clk_divider_flags, const struct clk_div_table *table, in clk_register_pll_div() argument
828 pll_div->div.flags = clk_divider_flags; in clk_register_pll_div()
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| /drivers/clk/imx/ |
| A D | clk-divider-gate.c | 178 u8 shift, u8 width, u8 clk_divider_flags, in imx_clk_hw_divider_gate() argument
193 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) in imx_clk_hw_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
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| A D | clk.h | 483 u8 clk_divider_flags, const struct clk_div_table *table,
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| /drivers/clk/tegra/ |
| A D | clk-divider.c | 136 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, in tegra_clk_register_divider() argument
161 divider->flags = clk_divider_flags; in tegra_clk_register_divider()
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| A D | clk.h | 136 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
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| /drivers/clk/xilinx/ |
| A D | clk-xlnx-clock-wizard.c | 790 u8 clk_divider_flags, in clk_wzrd_register_divf() argument
815 div->flags = clk_divider_flags; in clk_wzrd_register_divf()
834 u8 clk_divider_flags, in clk_wzrd_ver_register_divider() argument
848 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) in clk_wzrd_ver_register_divider()
862 div->flags = clk_divider_flags; in clk_wzrd_ver_register_divider()
880 u8 clk_divider_flags, in clk_wzrd_register_divider() argument
894 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) in clk_wzrd_register_divider()
908 div->flags = clk_divider_flags; in clk_wzrd_register_divider()
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| /drivers/clk/mediatek/ |
| A D | clk-mt8167-apmixedsys.c | 84 .clk_divider_flags = _flag, \
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| A D | clk-mtk.h | 192 unsigned char clk_divider_flags; member
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| A D | clk-mt8365.c | 549 .clk_divider_flags = _flags, \
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| A D | clk-mtk.c | 419 mcd->div_width, mcd->clk_divider_flags, lock); in mtk_clk_register_dividers()
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| /drivers/clk/ti/ |
| A D | adpll.c | 240 u8 clk_divider_flags) in ti_adpll_init_divider() argument
252 reg, shift, width, clk_divider_flags, in ti_adpll_init_divider()
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