| /drivers/clk/st/ |
| A D | clk-flexgen.c | 150 mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate); in flexgen_recalc_rate()
152 return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate); in flexgen_recalc_rate()
185 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
186 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
188 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
189 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
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| /drivers/clk/microchip/ |
| A D | clk-mpfs.c | 182 .output.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
230 .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
254 CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
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| A D | clk-mpfs-ccc.c | 172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); in mpfs_ccc_register_outputs()
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| /drivers/clk/imx/ |
| A D | clk-composite-93.c | 98 return clk_divider_ops.recalc_rate(hw, parent_rate); in imx93_clk_composite_divider_recalc_rate()
104 return clk_divider_ops.determine_rate(hw, req); in imx93_clk_composite_divider_determine_rate()
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| A D | clk-fixup-div.c | 115 fixup_div->ops = &clk_divider_ops; in imx_clk_hw_fixup_divider()
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| A D | clk-busy.c | 96 busy->div_ops = &clk_divider_ops; in imx_clk_hw_busy_divider()
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| A D | clk-divider-gate.c | 70 return clk_divider_ops.determine_rate(hw, req); in clk_divider_determine_rate()
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| A D | clk-composite-8m.c | 253 divider_ops = &clk_divider_ops; in __imx8m_clk_hw_composite()
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| /drivers/clk/mmp/ |
| A D | clk-audio.c | 265 &priv->sspa_mux.hw, &clk_divider_ops, in register_clocks()
287 &priv->sspa_mux.hw, &clk_divider_ops, 0); in register_clocks()
318 &priv->sspa1_mux.hw, &clk_divider_ops, 0); in register_clocks()
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| /drivers/clk/ |
| A D | clk-fsl-sai.c | 62 &clk_divider_ops, in fsl_sai_clk_probe()
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| A D | clk-divider.c | 528 const struct clk_ops clk_divider_ops = { variable
534 EXPORT_SYMBOL_GPL(clk_divider_ops);
572 init.ops = &clk_divider_ops; in __clk_hw_register_divider()
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| A D | clk-stm32h7.c | 396 gcfg->div->ops : &clk_divider_ops; in get_cfg_composite_div()
844 return clk_divider_ops.recalc_rate(hw, parent_rate); in odf_divider_recalc_rate()
850 return clk_divider_ops.determine_rate(hw, req); in odf_divider_determine_rate()
867 ret = clk_divider_ops.set_rate(hw, rate, parent_rate); in odf_divider_set_rate()
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| A D | clk-stm32f4.c | 766 return clk_divider_ops.recalc_rate(hw, parent_rate); in stm32f4_pll_div_recalc_rate()
772 return clk_divider_ops.determine_rate(hw, req); in stm32f4_pll_div_determine_rate()
788 ret = clk_divider_ops.set_rate(hw, rate, parent_rate); in stm32f4_pll_div_set_rate()
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| /drivers/clk/sunxi/ |
| A D | clk-sun8i-mbus.c | 79 &div->hw, &clk_divider_ops, in sun8i_a23_mbus_setup()
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| A D | clk-a10-ve.c | 122 &div->hw, &clk_divider_ops, in sun4i_ve_clk_setup()
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| A D | clk-sun4i-display.c | 161 data->has_div ? &clk_divider_ops : NULL, in sun4i_a10_display_init()
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| /drivers/clk/mxs/ |
| A D | clk-div.c | 96 div->ops = &clk_divider_ops; in mxs_clk_div()
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| /drivers/spi/ |
| A D | spi-meson-spicc.c | 796 return clk_divider_ops.recalc_rate(hw, parent_rate); in meson_spicc_pow2_recalc_rate()
808 return clk_divider_ops.determine_rate(hw, req); in meson_spicc_pow2_determine_rate()
820 return clk_divider_ops.set_rate(hw, rate, parent_rate); in meson_spicc_pow2_set_rate()
941 init.ops = &clk_divider_ops; in meson_spicc_enh_clk_init()
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| /drivers/clk/davinci/ |
| A D | pll.c | 240 const struct clk_ops *divider_ops = &clk_divider_ops; in davinci_pll_div_register()
617 ÷r->hw, &clk_divider_ops, in davinci_pll_obsclk_register()
679 const struct clk_ops *divider_ops = &clk_divider_ops; in davinci_pll_sysclk_register()
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| /drivers/mmc/host/ |
| A D | meson-mx-sdhc-clkc.c | 120 &clk_divider_ops, in meson_mx_sdhc_register_clkc()
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| /drivers/clk/renesas/ |
| A D | rcar-cpg-lib.c | 164 &rpc->div.hw, &clk_divider_ops, in cpg_rpc_clk_register()
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| A D | rcar-gen2-cpg.c | 237 &div->hw, &clk_divider_ops, in cpg_adsp_clk_register()
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| /drivers/net/ethernet/stmicro/stmmac/ |
| A D | dwmac-meson8b.c | 185 &clk_divider_ops, in meson8b_init_rgmii_tx_clk()
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| /drivers/clk/stm32/ |
| A D | clk-stm32mp1.c | 657 div_ops = &clk_divider_ops; in clk_stm32_register_composite()
1077 return clk_divider_ops.recalc_rate(hw, parent_rate); in clk_divider_rtc_recalc_rate()
1086 return clk_divider_ops.set_rate(hw, rate, parent_rate); in clk_divider_rtc_set_rate()
1094 return clk_divider_ops.determine_rate(hw, req); in clk_divider_rtc_determine_rate()
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| /drivers/pwm/ |
| A D | pwm-meson.c | 415 init.ops = &clk_divider_ops; in meson_pwm_init_clocks_meson8b()
|