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Searched refs:clk_mgr_base (Results 1 – 25 of 31) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c115 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
119 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
165 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); in dcn3_init_clocks()
199 struct dc *dc = clk_mgr_base->ctx->dc; in dcn3_update_clocks()
214 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn3_update_clocks()
219 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn3_update_clocks()
249 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn3_update_clocks()
271 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
320 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn3_update_clocks()
369 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
[all …]
A Ddcn30m_clk_mgr.c31 uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set) in dcn30m_set_smartmux_switch() argument
33 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn30m_set_smartmux_switch()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c222 if (!clk_mgr_base->bw_params) in dcn401_init_clocks()
308 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); in dcn401_init_clocks()
765 struct clk_mgr *clk_mgr_base, in dcn401_build_update_bandwidth_clocks_sequence() argument
887 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways; in dcn401_build_update_bandwidth_clocks_sequence()
899 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence()
1078 struct clk_mgr *clk_mgr_base, in dcn401_build_update_display_clocks_sequence() argument
1105 clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk; in dcn401_build_update_display_clocks_sequence()
1106 clk_mgr_base->clks.actual_dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn401_build_update_display_clocks_sequence()
1108 clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk; in dcn401_build_update_display_clocks_sequence()
1109 clk_mgr_base->clks.actual_dppclk_khz = clk_mgr_base->clks.dppclk_khz; in dcn401_build_update_display_clocks_sequence()
[all …]
A Ddcn401_clk_mgr.h107 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);
108 bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);
115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks()
260 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); in dcn32_init_clocks()
627 struct dc *dc = clk_mgr_base->ctx->dc; in dcn32_update_clocks()
639 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn32_update_clocks()
661 …clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_suppo… in dcn32_update_clocks()
670 …if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_s… in dcn32_update_clocks()
696 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn32_update_clocks()
697 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways; in dcn32_update_clocks()
805 clk_mgr_base->clks.ref_dtbclk_khz = in dcn32_update_clocks()
1040 …clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mh… in dcn32_get_memclk_states_from_smu()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c90 struct dc *dc = clk_mgr_base->ctx->dc; in rn_set_low_power_state()
137 struct dc *dc = clk_mgr_base->ctx->dc; in rn_update_clocks()
208 …clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispc… in rn_update_clocks()
218 clk_mgr_base->clks.dppclk_khz, in rn_update_clocks()
221 clk_mgr_base->clks.actual_dppclk_khz = in rn_update_clocks()
228 clk_mgr_base->clks.actual_dppclk_khz, in rn_update_clocks()
234 clk_mgr_base->clks.actual_dppclk_khz = in rn_update_clocks()
241 clk_mgr_base->clks.actual_dppclk_khz, in rn_update_clocks()
249 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in rn_update_clocks()
519 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.c84 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, in dcn201_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn201_update_clocks()
90 struct dc *dc = clk_mgr_base->ctx->dc; in dcn201_update_clocks()
101 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
113 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn201_update_clocks()
117 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
124 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
131 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn201_update_clocks()
136 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn201_update_clocks()
141 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn201_update_clocks()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c116 struct dc *dc = clk_mgr_base->ctx->dc; in dcn31_disable_otg_wa()
134 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, in dcn31_update_clocks() argument
141 struct dc *dc = clk_mgr_base->ctx->dc; in dcn31_update_clocks()
164 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()
190 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()
203 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn31_update_clocks()
225 dcn31_disable_otg_wa(clk_mgr_base, context, true); in dcn31_update_clocks()
229 dcn31_disable_otg_wa(clk_mgr_base, context, false); in dcn31_update_clocks()
253 clk_mgr_base->clks.dcfclk_deep_sleep_khz; in dcn31_update_clocks()
637 struct dc *dc = clk_mgr_base->ctx->dc; in dcn31_set_low_power_state()
[all …]
A Ddcn31_clk_mgr.h45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c216 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, in dcn2_update_clocks() argument
222 struct dc *dc = clk_mgr_base->ctx->dc; in dcn2_update_clocks()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
242 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
276 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn2_update_clocks()
284 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn2_update_clocks()
339 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn2_update_clocks()
511 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { in dcn2_notify_link_rate_change()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr.c187 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, in rv1_update_clocks() argument
192 struct dc *dc = clk_mgr_base->ctx->dc; in rv1_update_clocks()
224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
225 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
227 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) in rv1_update_clocks()
231 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks()
240 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; in rv1_update_clocks()
246 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in rv1_update_clocks()
275 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in rv1_update_clocks()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c105 struct dc *dc = clk_mgr_base->ctx->dc; in dcn316_disable_otg_wa()
128 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) in dcn316_enable_pme_wa() argument
142 struct dc *dc = clk_mgr_base->ctx->dc; in dcn316_update_clocks()
159 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn316_update_clocks()
172 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn316_update_clocks()
178 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn316_update_clocks()
186 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn316_update_clocks()
191 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn316_update_clocks()
208 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn316_update_clocks()
223 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn316_update_clocks()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce_get_dp_ref_freq_khz() argument
131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz()
155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce12_get_dp_ref_freq_khz() argument
195 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state() argument
230 struct clk_mgr *clk_mgr_base, in dce_set_clock() argument
235 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce_set_clock()
249 if (clk_mgr_base->ctx->dce_version == DCE_VERSION_6_0 || in dce_set_clock()
250 clk_mgr_base->ctx->dce_version == DCE_VERSION_6_4) in dce_set_clock()
402 static void dce_update_clocks(struct clk_mgr *clk_mgr_base, in dce_update_clocks() argument
423 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce_update_clocks()
[all …]
A Ddce_clk_mgr.h34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
36 struct clk_mgr *clk_mgr_base,
51 struct clk_mgr *clk_mgr_base,
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c102 struct dc *dc = clk_mgr_base->ctx->dc; in dcn315_disable_otg_wa()
132 struct dc *dc = clk_mgr_base->ctx->dc; in dcn315_update_clocks()
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks()
163 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn315_update_clocks()
169 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks()
184 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn315_update_clocks()
201 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn315_update_clocks()
209 dcn315_disable_otg_wa(clk_mgr_base, context, true); in dcn315_update_clocks()
216 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn315_update_clocks()
217 dcn315_disable_otg_wa(clk_mgr_base, context, false); in dcn315_update_clocks()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
A Ddce112_clk_mgr.c70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock() argument
72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock()
74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce112_set_clock()
75 struct dc *dc = clk_mgr_base->ctx->dc; in dce112_set_clock()
104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && in dce112_set_clock()
105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) in dce112_set_clock()
191 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, in dce112_update_clocks() argument
195 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks()
212 patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce112_update_clocks()
213 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.c151 struct dc *dc = clk_mgr_base->ctx->dc; in dcn314_disable_otg_wa()
174 bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) in dcn314_is_spll_ssc_enabled() argument
205 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, in dcn314_update_clocks() argument
212 struct dc *dc = clk_mgr_base->ctx->dc; in dcn314_update_clocks()
235 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn314_update_clocks()
248 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn314_update_clocks()
261 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn314_update_clocks()
275 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn314_update_clocks()
292 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn314_update_clocks()
299 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn314_update_clocks()
[all …]
A Ddcn314_clk_mgr.h53 bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);
57 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
A Ddce120_clk_mgr.c84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_update_clocks()
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
109 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
117 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
119 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce12_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
A Ddce60_clk_mgr.c83 static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce60_get_dp_ref_freq_khz() argument
85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_get_dp_ref_freq_khz()
120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, in dce60_update_clocks() argument
124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_update_clocks()
132 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce60_update_clocks()
136 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce60_update_clocks()
140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
141 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce60_update_clocks()
142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks()
144 dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce60_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c192 struct dc *dc = clk_mgr_base->ctx->dc; in dcn35_disable_otg_wa()
377 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, in dcn35_update_clocks() argument
384 struct dc *dc = clk_mgr_base->ctx->dc; in dcn35_update_clocks()
414 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn35_update_clocks()
440 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn35_update_clocks()
458 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn35_update_clocks()
475 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn35_update_clocks()
500 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { in dcn35_update_clocks()
526 clk_mgr_base->clks.dcfclk_deep_sleep_khz; in dcn35_update_clocks()
601 if (clk_mgr_base->ctx->dce_version == DCN_VERSION_3_51) { in dcn35_is_spll_ssc_enabled()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c95 static void vg_update_clocks(struct clk_mgr *clk_mgr_base, in vg_update_clocks() argument
101 struct dc *dc = clk_mgr_base->ctx->dc; in vg_update_clocks()
128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in vg_update_clocks()
138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in vg_update_clocks()
143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks()
160 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in vg_update_clocks()
165 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in vg_update_clocks()
238 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) in vg_dump_clk_registers() argument
245 vg_dump_clk_registers_internal(&internal, clk_mgr_base); in vg_dump_clk_registers()
370 static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base) in vg_enable_pme_wa() argument
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c249 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, in dce11_update_clocks() argument
253 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce11_update_clocks()
261 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce11_update_clocks()
265 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce11_update_clocks()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
273 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce11_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/
A Dclk_mgr.c386 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) in dc_destroy_clk_mgr() argument
388 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr()
391 switch (clk_mgr_base->ctx->asic_id.chip_family) { in dc_destroy_clk_mgr()
393 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
395 } else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
398 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
404 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) in dc_destroy_clk_mgr()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h299 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);
336 int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base);
342 unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);

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