Home
last modified time | relevance | path

Searched refs:clk_names (Results 1 – 25 of 54) sorted by relevance

123

/drivers/clk/berlin/
A Dbg2.c102 static const char *clk_names[] = { variable
530 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
535 clk_names[MEMPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
540 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2_clock_setup()
549 clk_names[REFCLK], avpll_flags, 0); in berlin2_clock_setup()
576 parent_names[0] = clk_names[SYSPLL]; in berlin2_clock_setup()
577 parent_names[1] = clk_names[REFCLK]; in berlin2_clock_setup()
584 parent_names[0] = clk_names[MEMPLL]; in berlin2_clock_setup()
585 parent_names[1] = clk_names[REFCLK]; in berlin2_clock_setup()
592 parent_names[0] = clk_names[CPUPLL]; in berlin2_clock_setup()
[all …]
A Dbg2q.c51 static const char *clk_names[] = { variable
313 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2q_clock_setup()
315 clk_names[REFCLK] = __clk_get_name(clk); in berlin2q_clock_setup()
321 clk_names[SYSPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
326 clk_names[CPUPLL], clk_names[REFCLK], 0); in berlin2q_clock_setup()
343 parent_names[k] = clk_names[dd->parent_ids[k]]; in berlin2q_clock_setup()
361 clk_hw_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL], in berlin2q_clock_setup()
/drivers/usb/dwc3/
A Ddwc3-exynos.c23 const char *clk_names[DWC3_EXYNOS_MAX_CLOCKS]; member
31 const char **clk_names; member
55 exynos->clk_names = (const char **)driver_data->clk_names; in dwc3_exynos_probe()
61 exynos->clks[i] = devm_clk_get(dev, exynos->clk_names[i]); in dwc3_exynos_probe()
64 exynos->clk_names[i]); in dwc3_exynos_probe()
149 .clk_names = { "link_aclk" },
155 .clk_names = { "usbdrd30" },
161 .clk_names = { "aclk", "susp_clk", "pipe_pclk", "phyclk" },
173 .clk_names = { "bus_early", "ref", "ctrl" },
179 .clk_names = { "bus_early", "ref" },
[all …]
/drivers/pmdomain/imx/
A Dimx8m-blk-ctrl.c41 const char * const *clk_names; member
233 domain->clks[j].id = data->clk_names[j]; in imx8m_blk_ctrl_probe()
453 .clk_names = (const char *[]){ "g1", },
461 .clk_names = (const char *[]){ "g2", },
469 .clk_names = (const char *[]){ "h1", },
487 .clk_names = (const char *[]){ "g1", },
497 .clk_names = (const char *[]){ "g2", },
507 .clk_names = (const char *[]){ "vc8000e", },
797 .clk_names = (const char *[]){ "phy", },
852 .clk_names = (const char *[]){ "g1", },
[all …]
A Dimx93-blk-ctrl.c72 const char * const *clk_names; member
90 const char * const *clk_names; member
238 bc->clks[i].id = bc_data->clk_names[i]; in imx93_blk_ctrl_probe()
255 domain->clks[j].id = data->clk_names[j]; in imx93_blk_ctrl_probe()
328 .clk_names = (const char *[]){ "dsi" },
335 .clk_names = (const char *[]){ "cam", "csi" },
342 .clk_names = (const char *[]){ "pxp" },
363 .clk_names = (const char *[]){ "disp", "lcdif" },
379 .clk_names = (const char *[]){ "isi" },
424 .clk_names = (const char *[]){ "axi", "apb", "nic", },
A Dimx8mp-blk-ctrl.c51 const char * const *clk_names; member
258 .clk_names = (const char *[]){ "usb" },
274 .clk_names = (const char *[]){ "pcie" },
454 .clk_names = (const char *[]){ "apb" },
468 .clk_names = (const char *[]){ "apb" },
474 .clk_names = (const char *[]){ "apb" },
480 .clk_names = (const char *[]){ "apb" },
492 .clk_names = (const char *[]){ "apb", "ref_24m" },
498 .clk_names = (const char *[]){ "axi", "apb" },
506 .clk_names = (const char *[]){ "axi", "apb" },
[all …]
/drivers/media/platform/samsung/s5p-mfc/
A Ds5p_mfc_pm.c23 pm->clk_names = dev->variant->clk_names; in s5p_mfc_init_pm()
29 pm->clocks[i] = devm_clk_get(pm->device, pm->clk_names[i]); in s5p_mfc_init_pm()
37 pm->clk_names[i]); in s5p_mfc_init_pm()
77 dev->pm.clk_names[i]); in s5p_mfc_power_on()
/drivers/ufs/host/
A Dufshcd-pltfrm.c268 const char **clk_names; in ufshcd_parse_operating_points() local
287 clk_names = devm_kcalloc(dev, cnt + 1, sizeof(*clk_names), GFP_KERNEL); in ufshcd_parse_operating_points()
288 if (!clk_names) in ufshcd_parse_operating_points()
297 &clk_names[i]); in ufshcd_parse_operating_points()
305 clki->name = devm_kstrdup(dev, clk_names[i], GFP_KERNEL); in ufshcd_parse_operating_points()
309 if (!strcmp(clk_names[i], "ref_clk")) in ufshcd_parse_operating_points()
315 config.clk_names = clk_names, in ufshcd_parse_operating_points()
/drivers/media/platform/verisilicon/
A Drockchip_vpu_hw.c674 .clk_names = rockchip_vpu_clk_names,
699 .clk_names = rk3066_vpu_clk_names,
719 .clk_names = rockchip_vpu_clk_names,
735 .clk_names = rockchip_vpu_clk_names,
757 .clk_names = rockchip_vpu_clk_names,
770 .clk_names = rockchip_vpu_clk_names,
784 .clk_names = rockchip_vpu_clk_names,
801 .clk_names = rockchip_vpu_clk_names,
816 .clk_names = rk3588_vpu981_vpu_clk_names,
A Dimx8m_vpu_hw.c356 .clk_names = imx8mq_clk_names,
373 .clk_names = imx8mq_g1_clk_names,
388 .clk_names = imx8mq_g2_clk_names,
400 .clk_names = imx8mq_g1_clk_names,
A Dstm32mp25_vpu_hw.c165 .clk_names = stm32mp25_vdec_clk_names,
184 .clk_names = stm32mp25_venc_clk_names,
/drivers/soc/tegra/
A Dcommon.c114 const char *clk_names[] = { NULL, NULL }; in devm_tegra_core_dev_init_opp_table() local
124 .clk_names = clk_names, in devm_tegra_core_dev_init_opp_table()
/drivers/gpu/drm/exynos/
A Dexynos_drm_mic.c92 static const char *const clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" }; variable
93 #define NUM_CLKS ARRAY_SIZE(clk_names)
363 clk_names[i]); in exynos_mic_resume()
413 mic->clks[i] = devm_clk_get(dev, clk_names[i]); in exynos_mic_probe()
416 clk_names[i]); in exynos_mic_probe()
A Dexynos_drm_gsc.c107 const char *const *clk_names; member
127 const char *clk_names[GSC_MAX_CLOCKS]; member
1233 ctx->clk_names = driver_data->clk_names; in gsc_probe()
1265 ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]); in gsc_probe()
1268 ctx->clk_names[i]); in gsc_probe()
1383 .clk_names = {"gscl"},
1390 .clk_names = {"gscl"},
1397 .clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
/drivers/gpu/drm/msm/hdmi/
A Dhdmi_phy.c41 clk = msm_clk_get(phy->pdev, cfg->clk_names[i]); in msm_hdmi_phy_resource_init()
45 cfg->clk_names[i], ret); in msm_hdmi_phy_resource_init()
77 cfg->clk_names[i], ret); in msm_hdmi_phy_resource_enable()
A Dhdmi_phy_8x74.c42 .clk_names = hdmi_phy_8x74_clk_names,
A Dhdmi_phy_8960.c49 .clk_names = hdmi_phy_8960_clk_names,
/drivers/soc/samsung/
A Dexynos-usi.c60 const char * const *clk_names; /* clock names to assert */ member
108 .clk_names = exynos850_usi_clk_names,
117 .clk_names = exynos850_usi_clk_names,
283 usi->clks[i].id = usi->data->clk_names[i]; in exynos_usi_get_clocks()
/drivers/power/sequencing/
A Dpwrseq-thead-gpu.c121 static const char *const clk_names[] = { "core", "sys" }; in pwrseq_thead_gpu_match() local
147 ctx->num_clks = ARRAY_SIZE(clk_names); in pwrseq_thead_gpu_match()
153 ctx->clks[i].id = clk_names[i]; in pwrseq_thead_gpu_match()
/drivers/phy/
A Dphy-snps-eusb2.c159 const char * const *clk_names; member
363 .clk_names = exynos_eusb2_hsphy_clock_names,
452 .clk_names = qcom_eusb2_hsphy_clock_names,
559 phy->clks[i].id = phy->data->clk_names[i]; in snps_eusb2_hsphy_probe()
/drivers/crypto/
A Ds5p-sss.c240 const char *clk_names[2]; member
387 .clk_names = { "secss", },
393 .clk_names = { "secss", },
399 .clk_names = { "aclk", "pclk", },
2178 pdata->clk = devm_clk_get(dev, variant->clk_names[0]); in s5p_aes_probe()
2182 variant->clk_names[0]); in s5p_aes_probe()
2187 variant->clk_names[0], err); in s5p_aes_probe()
2191 if (variant->clk_names[1]) { in s5p_aes_probe()
2192 pdata->pclk = devm_clk_get(dev, variant->clk_names[1]); in s5p_aes_probe()
2196 variant->clk_names[1]); in s5p_aes_probe()
[all …]
/drivers/phy/samsung/
A Dphy-exynos5-usbdrd.c429 const char * const *clk_names; member
1733 phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i]; in exynos5_usbdrd_phy_clk_handle()
1944 .clk_names = exynos5_clk_names,
1958 .clk_names = exynos5_clk_names,
1970 .clk_names = exynos5_clk_names,
1983 .clk_names = exynos5_clk_names,
1995 .clk_names = exynos5_clk_names,
2008 .clk_names = exynos5_clk_names,
2020 .clk_names = exynos5_clk_names,
2049 .clk_names = exynos5_clk_names,
[all …]
/drivers/clk/ti/
A Dclk.c546 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) in omap2_clk_enable_init_clocks() argument
552 init_clk = clk_get(NULL, clk_names[i]); in omap2_clk_enable_init_clocks()
554 clk_names[i])) in omap2_clk_enable_init_clocks()
/drivers/media/platform/samsung/exynos-gsc/
A Dgsc-core.c1046 .clk_names = { "gscl" },
1058 .clk_names = { "gscl" },
1068 .clk_names = { "gscl" },
1079 .clk_names = { "pclk", "aclk", "aclk_xiu", "aclk_gsclbend" },
1147 gsc->clock[i] = devm_clk_get(dev, drv_data->clk_names[i]); in gsc_probe()
1150 drv_data->clk_names[i]); in gsc_probe()
1159 drv_data->clk_names[i]); in gsc_probe()
/drivers/clk/
A Dclk-sparx5.c31 static const char *clk_names[N_CLOCKS] = { variable
268 init.name = clk_names[i]; in s5_clk_probe()

Completed in 68 milliseconds

123