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Searched refs:clk_phase (Results 1 – 2 of 2) sorted by relevance

/drivers/mmc/host/
A Ddw_mmc-pltfm.c74 u32 clk_phase[2] = {0}, reg_offset, reg_shift; in dw_mci_socfpga_priv_init() local
77 rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); in dw_mci_socfpga_priv_init()
90 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) in dw_mci_socfpga_priv_init()
91 clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; in dw_mci_socfpga_priv_init()
93 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); in dw_mci_socfpga_priv_init()
A Dsdhci-of-arasan.c1241 u32 clk_phase[2] = {0}; in arasan_dt_read_clk_phase() local
1248 ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0], in arasan_dt_read_clk_phase()
1258 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1259 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()

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