Searched refs:clk_post (Results 1 – 10 of 10) sorted by relevance
| /drivers/gpu/drm/msm/dsi/phy/ |
| A D | dsi_phy.c | 114 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0, in msm_dsi_dphy_timing_calc()
136 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc()
226 timing->shared_timings.clk_post = in msm_dsi_dphy_timing_calc_v2()
250 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v2()
334 timing->shared_timings.clk_post = in msm_dsi_dphy_timing_calc_v3()
360 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v3()
447 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false); in msm_dsi_dphy_timing_calc_v4()
462 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v4()
501 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 80, 0, false); in msm_dsi_cphy_timing_calc_v4()
508 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_cphy_timing_calc_v4()
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| A D | dsi_phy_7nm.c | 1101 writel(timing->shared_timings.clk_post, in dsi_7nm_phy_enable()
1122 writel(timing->shared_timings.clk_post, in dsi_7nm_phy_enable()
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| /drivers/phy/ |
| A D | phy-core-mipi-dphy.c | 40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
120 if (cfg->clk_post < (60000 + 52 * ui)) in phy_mipi_dphy_config_validate()
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| /drivers/phy/rockchip/ |
| A D | phy-rockchip-inno-dsidphy.c | 372 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; in inno_dsidphy_mipi_mode_enable() local
430 clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
504 T_CLK_POST_CNT_HI(clk_post >> 4)); in inno_dsidphy_mipi_mode_enable()
506 T_CLK_POST_CNT_LO(clk_post)); in inno_dsidphy_mipi_mode_enable()
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| A D | phy-rockchip-samsung-dcphy.c | 321 u8 clk_post; member
1257 val = T_CLK_POST(timing->clk_post); in samsung_mipi_dphy_clk_lane_timing_init()
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| /drivers/gpu/drm/msm/dsi/ |
| A D | dsi.h | 130 u32 clk_post; member
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| A D | dsi_host.c | 850 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | in dsi_ctrl_enable()
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| /drivers/phy/amlogic/ |
| A D | phy-meson-axg-mipi-dphy.c | 249 (DIV_ROUND_UP(priv->config.clk_post + in phy_meson_axg_mipi_dphy_power_on()
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| /drivers/gpu/drm/bridge/ |
| A D | samsung-dsim.c | 754 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; in samsung_dsim_set_phy_ctrl() local
784 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock); in samsung_dsim_set_phy_ctrl()
822 DSIM_PHYTIMING1_CLK_POST(clk_post) | in samsung_dsim_set_phy_ctrl()
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| /drivers/media/i2c/ |
| A D | tc358746.c | 651 val = tc358746_ps_to_cnt(cfg->clk_post, hs_byte_clk); in tc358746_apply_dphy_config()
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Completed in 41 milliseconds