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Searched refs:clk_state (Results 1 – 8 of 8) sorted by relevance

/drivers/slimbus/
A Dsched.c40 if (sched->clk_state == SLIM_CLK_ACTIVE) { in slim_ctrl_clk_pause()
63 if (sched->clk_state == SLIM_CLK_PAUSED && ctrl->wakeup) in slim_ctrl_clk_pause()
66 sched->clk_state = SLIM_CLK_ACTIVE; in slim_ctrl_clk_pause()
73 if (ctrl->sched.clk_state == SLIM_CLK_PAUSED) { in slim_ctrl_clk_pause()
89 sched->clk_state = SLIM_CLK_ENTERING_PAUSE; in slim_ctrl_clk_pause()
112 sched->clk_state = SLIM_CLK_ACTIVE; in slim_ctrl_clk_pause()
114 sched->clk_state = SLIM_CLK_PAUSED; in slim_ctrl_clk_pause()
A Dmessaging.c121 if (ctrl->sched.clk_state == SLIM_CLK_ENTERING_PAUSE && in slim_do_transfer()
129 if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) { in slim_do_transfer()
131 ctrl->sched.clk_state, ret); in slim_do_transfer()
A Dcore.c489 if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) { in slim_device_report_present()
491 ctrl->sched.clk_state, ret); in slim_device_report_present()
A Dslimbus.h178 enum slim_clk_state clk_state; member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c293 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info() local
297 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; in dce_clock_read_integrated_info()
301 clk_state = DM_PP_CLOCKS_STATE_LOW; in dce_clock_read_integrated_info()
305 clk_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce_clock_read_integrated_info()
309 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; in dce_clock_read_integrated_info()
313 clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info()
321 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = in dce_clock_read_integrated_info()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clk_mgr.c365 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info() local
369 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; in dce_clock_read_integrated_info()
373 clk_state = DM_PP_CLOCKS_STATE_LOW; in dce_clock_read_integrated_info()
377 clk_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce_clock_read_integrated_info()
381 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; in dce_clock_read_integrated_info()
385 clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info()
392 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = in dce_clock_read_integrated_info()
/drivers/firmware/arm_scmi/
A Dclock.c39 enum clk_state { enum
168 u32 clk_id, enum clk_state state,
631 enum clk_state state, in scmi_clock_config_set()
722 enum clk_state state, in scmi_clock_config_set_v2()
/drivers/mtd/nand/raw/
A Ds3c2410.c163 enum s3c_nand_clk_state clk_state; member
227 if (info->clk_state == CLOCK_ENABLE) { in s3c2410_nand_clk_set_state()
235 info->clk_state = new_state; in s3c2410_nand_clk_set_state()

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