| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/ |
| A D | dml2_mcg_dcn4.c | 54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
169 if (soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.dcfclk.num_clk_values && in build_min_clock_table()
170 soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.uclk.num_clk_values) in build_min_clock_table()
179 …min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dis… in build_min_clock_table()
180 …min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppcl… in build_min_clock_table()
181 …min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dsccl… in build_min_clock_table()
182 …min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbcl… in build_min_clock_table()
183 …min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phycl… in build_min_clock_table()
189 …min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfcl… in build_min_clock_table()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| A D | dcn321_fpu.c | 380 if (bw_params->clk_table.entries[i].memclk_mhz > 0) { in build_synthetic_soc_states()
385 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { in build_synthetic_soc_states()
390 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) { in build_synthetic_soc_states()
408 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; in build_synthetic_soc_states()
756 num_uclk_states = bw_params->clk_table.num_entries; in dcn321_update_bw_bounding_box_fpu()
772 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
830 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { in dcn321_update_bw_bounding_box_fpu()
835 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { in dcn321_update_bw_bounding_box_fpu()
839 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) in dcn321_update_bw_bounding_box_fpu()
864 if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) { in dcn321_update_bw_bounding_box_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.c | 257 .clk_table = {
409 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn315_build_watermark_ranges()
489 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn315_clk_mgr_helper_populate_bw_params()
508 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
509 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
510 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
520 bw_params->clk_table.entries[i].wck_ratio = 1; in dcn315_clk_mgr_helper_populate_bw_params()
529 bw_params->clk_table.entries[i].wck_ratio = 1; in dcn315_clk_mgr_helper_populate_bw_params()
537 bw_params->clk_table.num_entries = i; in dcn315_clk_mgr_helper_populate_bw_params()
543 if (!bw_params->clk_table.entries[i].fclk_mhz) { in dcn315_clk_mgr_helper_populate_bw_params()
[all …]
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| /drivers/clk/samsung/ |
| A D | clk-s5pv210-audss.c | 70 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
85 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
114 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
130 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
133 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
137 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
158 clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss", in s5pv210_audss_clk_probe()
163 if (IS_ERR(clk_table[i])) { in s5pv210_audss_clk_probe()
165 ret = PTR_ERR(clk_table[i]); in s5pv210_audss_clk_probe()
185 if (!IS_ERR(clk_table[i])) in s5pv210_audss_clk_probe()
[all …]
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| A D | clk-exynos-audss.c | 131 struct clk_hw **clk_table; in exynos_audss_clk_probe() local
153 clk_table = clk_data->hws; in exynos_audss_clk_probe()
195 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", in exynos_audss_clk_probe()
204 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()
212 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", in exynos_audss_clk_probe()
216 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
220 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
224 clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus", in exynos_audss_clk_probe()
236 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma", in exynos_audss_clk_probe()
242 if (IS_ERR(clk_table[i])) { in exynos_audss_clk_probe()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 593 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box() local
607 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box()
633 2 * clk_table->entries[i].wck_ratio; in dcn31_update_bw_bounding_box()
651 if (clk_table->num_entries) in dcn31_update_bw_bounding_box()
670 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn315_update_bw_bounding_box() local
683 ASSERT(clk_table->num_entries); in dcn315_update_bw_bounding_box()
732 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn316_update_bw_bounding_box() local
746 ASSERT(clk_table->num_entries); in dcn316_update_bw_bounding_box()
760 clk_table->entries[i].dcfclk_mhz) { in dcn316_update_bw_bounding_box()
773 2 * clk_table->entries[i].wck_ratio; in dcn316_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.c | 397 .clk_table = {
512 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
622 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn314_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
668 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
669 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
699 bw_params->clk_table.num_entries = i--; in dcn314_clk_mgr_helper_populate_bw_params()
715 if (!bw_params->clk_table.entries[i].fclk_mhz) { in dcn314_clk_mgr_helper_populate_bw_params()
720 if (!bw_params->clk_table.entries[i].dcfclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()
722 if (!bw_params->clk_table.entries[i].socclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
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| /drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0_0_ppt.c | 649 *freq = clk_table->VClocks0[dpm_level]; in smu_v14_0_1_get_dpm_freq_by_index()
703 *freq = clk_table->VClocks[dpm_level]; in smu_v14_0_0_get_dpm_freq_by_index()
708 *freq = clk_table->DClocks[dpm_level]; in smu_v14_0_0_get_dpm_freq_by_index()
824 *max = clk_table->MaxGfxClk; in smu_v14_0_1_get_dpm_ultimate_freq()
860 *min = clk_table->MinGfxClk; in smu_v14_0_1_get_dpm_ultimate_freq()
944 *max = clk_table->MaxGfxClk; in smu_v14_0_0_get_dpm_ultimate_freq()
976 *min = clk_table->MinGfxClk; in smu_v14_0_0_get_dpm_ultimate_freq()
1575 …clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClock… in smu_14_0_1_get_dpm_table()
1580 …clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[i… in smu_14_0_1_get_dpm_table()
1594 …clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClock… in smu_14_0_0_get_dpm_table()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 266 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn351_update_bw_bounding_box_fpu() local
350 if (clk_table->num_entries) in dcn351_update_bw_bounding_box_fpu()
391 clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
403 clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio; in dcn351_update_bw_bounding_box_fpu()
408 clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
410 clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
412 clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
414 clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
416 clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
418 clk_table->num_entries; in dcn351_update_bw_bounding_box_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 232 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn35_update_bw_bounding_box_fpu() local
316 if (clk_table->num_entries) in dcn35_update_bw_bounding_box_fpu()
357 clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
369 clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio; in dcn35_update_bw_bounding_box_fpu()
375 clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
377 clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
379 clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
381 clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
383 clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
385 clk_table->num_entries; in dcn35_update_bw_bounding_box_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| A D | dcn302_fpu.c | 220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
231 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
258 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_fpu_update_bw_bounding_box()
273 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
329 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn302_fpu_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| A D | dcn303_fpu.c | 216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
227 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
252 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_fpu_update_bw_bounding_box()
267 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
278 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
295 bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
335 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) in dcn303_fpu_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | dcn314_fpu.c | 184 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn314_update_bw_bounding_box_fpu() local
205 ASSERT(clk_table->num_entries); in dcn314_update_bw_bounding_box_fpu()
208 for (i = 0; i < clk_table->num_entries; ++i) { in dcn314_update_bw_bounding_box_fpu()
215 for (i = 0; i < clk_table->num_entries; i++) { in dcn314_update_bw_bounding_box_fpu()
223 if (clk_table->num_entries == 1) { in dcn314_update_bw_bounding_box_fpu()
232 if (clk_table->num_entries == 1 && in dcn314_update_bw_bounding_box_fpu()
240 if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio) in dcn314_update_bw_bounding_box_fpu()
241 …clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_… in dcn314_update_bw_bounding_box_fpu()
256 for (i = 0; i < clk_table->num_entries; i++) in dcn314_update_bw_bounding_box_fpu()
258 if (clk_table->num_entries) { in dcn314_update_bw_bounding_box_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_clk_mgr.c | 640 .clk_table = {
906 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn35_clk_mgr_helper_populate_bw_params()
970 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
971 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
972 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
981 bw_params->clk_table.entries[i].wck_ratio = in dcn35_clk_mgr_helper_populate_bw_params()
996 bw_params->clk_table.entries[i].dcfclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1006 bw_params->clk_table.num_entries = i--; in dcn35_clk_mgr_helper_populate_bw_params()
1009 bw_params->clk_table.entries[i].socclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1013 bw_params->clk_table.entries[i].dppclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
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| /drivers/clk/mmp/ |
| A D | clk.c | 13 struct clk **clk_table; in mmp_clk_init() local
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
175 unit->clk_table[clks[i].id] = clk; in mmp_register_div_clks()
[all …]
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | vega10_processpptables.c | 576 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_socclk_voltage_dependency_table()
578 if (!clk_table) in get_socclk_voltage_dependency_table()
637 *clk_table; in get_gfxclk_voltage_dependency_table() local
645 if (!clk_table) in get_gfxclk_voltage_dependency_table()
681 kfree(clk_table); in get_gfxclk_voltage_dependency_table()
700 *clk_table; in get_pix_clk_voltage_dependency_table() local
707 if (!clk_table) in get_pix_clk_voltage_dependency_table()
733 *clk_table; in get_dcefclk_voltage_dependency_table() local
758 clk_table = kzalloc(struct_size(clk_table, entries, num_entries), in get_dcefclk_voltage_dependency_table()
760 if (!clk_table) in get_dcefclk_voltage_dependency_table()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| A D | dcn401_clk_mgr.c | 245 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn401_init_clocks()
254 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn401_init_clocks()
264 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn401_init_clocks()
274 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn401_init_clocks()
283 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn401_init_clocks()
295 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn401_init_clocks()
301 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn401_init_clocks()
303 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz in dcn401_init_clocks()
836 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.… in dcn401_build_update_bandwidth_clocks_sequence()
1386 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, in dcn401_get_memclk_states_from_smu()
[all …]
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | smu_v13_0_5_ppt.c | 633 *count = clk_table->NumSocClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
636 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
639 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
642 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
645 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
661 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
668 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
673 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
678 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
755 *max = clk_table->MaxGfxClk; in smu_v13_0_5_get_dpm_ultimate_freq()
[all …]
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| A D | smu_v13_0_4_ppt.c | 431 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
438 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
443 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
448 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
476 *count = clk_table->NumSocClkLevelsEnabled; in smu_v13_0_4_get_dpm_level_count()
479 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_4_get_dpm_level_count()
482 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_4_get_dpm_level_count()
485 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_4_get_dpm_level_count()
488 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_4_get_dpm_level_count()
778 *max = clk_table->MaxGfxClk; in smu_v13_0_4_get_dpm_ultimate_freq()
[all …]
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| A D | yellow_carp_ppt.c | 767 *count = clk_table->NumSocClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
770 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
773 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
776 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
779 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
795 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
802 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
807 *freq = clk_table->VClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
812 *freq = clk_table->DClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
889 *max = clk_table->MaxGfxClk; in yellow_carp_get_dpm_ultimate_freq()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 207 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
2838 if (bw_params->clk_table.entries[i].memclk_mhz > 0) { in build_synthetic_soc_states()
2843 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { in build_synthetic_soc_states()
2848 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) { in build_synthetic_soc_states()
2866 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; in build_synthetic_soc_states()
3151 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn32_update_bw_bounding_box_fpu()
3169 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 && in dcn32_update_bw_bounding_box_fpu()
3206 num_uclk_states = bw_params->clk_table.num_entries; in dcn32_update_bw_bounding_box_fpu()
3222 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn32_update_bw_bounding_box_fpu()
3280 if (!bw_params->clk_table.entries[i].dtbclk_mhz) { in dcn32_update_bw_bounding_box_fpu()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.c | 134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
145 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
151 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
156 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
161 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
271 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
369 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
372 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
385 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_max_memclk()
[all …]
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| /drivers/clk/hisilicon/ |
| A D | clk.c | 31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 327 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_fpu_update_bw_bounding_box() local
340 ASSERT(clk_table->num_entries); in dcn301_fpu_update_bw_bounding_box()
341 for (i = 0; i < clk_table->num_entries; i++) { in dcn301_fpu_update_bw_bounding_box()
344 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_fpu_update_bw_bounding_box()
351 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_fpu_update_bw_bounding_box()
352 s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn301_fpu_update_bw_bounding_box()
353 s[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in dcn301_fpu_update_bw_bounding_box()
354 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_fpu_update_bw_bounding_box()
367 if (clk_table->num_entries) { in dcn301_fpu_update_bw_bounding_box()
368 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_fpu_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_clk_mgr.c | 264 .clk_table = {
371 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn316_build_watermark_ranges()
374 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges()
511 bw_params->clk_table.num_entries = j + 1; in dcn316_clk_mgr_helper_populate_bw_params()
530 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn316_clk_mgr_helper_populate_bw_params()
533 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn316_clk_mgr_helper_populate_bw_params()
536 bw_params->clk_table.entries[i].wck_ratio = 1; in dcn316_clk_mgr_helper_populate_bw_params()
540 bw_params->clk_table.entries[i].dcfclk_mhz = temp; in dcn316_clk_mgr_helper_populate_bw_params()
543 bw_params->clk_table.entries[i].socclk_mhz = temp; in dcn316_clk_mgr_helper_populate_bw_params()
545 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn316_clk_mgr_helper_populate_bw_params()
[all …]
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