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Searched refs:clk_type (Results 1 – 25 of 55) sorted by relevance

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/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c640 switch (clk_type) { in smu_v14_0_1_get_dpm_freq_by_index()
694 switch (clk_type) { in smu_v14_0_0_get_dpm_freq_by_index()
735 else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1) in smu_v14_0_common_get_dpm_freq_by_index()
746 switch (clk_type) { in smu_v14_0_0_clk_dpm_is_enabled()
849 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v14_0_1_get_dpm_ultimate_freq()
883 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v14_0_1_get_dpm_ultimate_freq()
965 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v14_0_0_get_dpm_ultimate_freq()
997 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v14_0_0_get_dpm_ultimate_freq()
1015 else if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1) in smu_v14_0_common_get_dpm_ultimate_freq()
1027 switch (clk_type) { in smu_v14_0_0_get_current_clk_freq()
[all …]
A Dsmu_v14_0.c1102 switch (clk_type) { in smu_v14_0_get_dpm_ultimate_freq()
1130 clk_type); in smu_v14_0_get_dpm_ultimate_freq()
1163 enum smu_clk_type clk_type, in smu_v14_0_set_soft_freq_limited_range() argument
1176 clk_type); in smu_v14_0_set_soft_freq_limited_range()
1222 clk_type); in smu_v14_0_set_hard_freq_limited_range()
1456 clk_type); in smu_v14_0_get_dpm_freq_by_index()
1475 enum smu_clk_type clk_type, in smu_v14_0_get_dpm_level_count() argument
1501 clk_type); in smu_v14_0_get_fine_grained_status()
1532 clk_type, in smu_v14_0_set_single_dpm_table()
1540 clk_type, in smu_v14_0_set_single_dpm_table()
[all …]
/drivers/gpu/drm/amd/display/dc/
A Ddm_services_types.h82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
91 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
92 (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_5_ppt.c600 switch (clk_type) { in smu_v13_0_5_get_current_clk_freq()
631 switch (clk_type) { in smu_v13_0_5_get_dpm_level_count()
664 switch (clk_type) { in smu_v13_0_5_get_dpm_freq_by_index()
703 switch (clk_type) { in smu_v13_0_5_clk_dpm_is_enabled()
752 switch (clk_type) { in smu_v13_0_5_get_dpm_ultimate_freq()
774 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_5_get_dpm_ultimate_freq()
804 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_5_get_dpm_ultimate_freq()
829 switch (clk_type) { in smu_v13_0_5_set_soft_freq_limited_range()
870 switch (clk_type) { in smu_v13_0_5_print_clk_levels()
945 switch (clk_type) { in smu_v13_0_5_force_clk_levels()
[all …]
A Dsmu_v13_0_4_ppt.c394 switch (clk_type) { in smu_v13_0_4_get_current_clk_freq()
434 switch (clk_type) { in smu_v13_0_4_get_dpm_freq_by_index()
474 switch (clk_type) { in smu_v13_0_4_get_dpm_level_count()
506 switch (clk_type) { in smu_v13_0_4_print_clk_levels()
726 switch (clk_type) { in smu_v13_0_4_clk_dpm_is_enabled()
775 switch (clk_type) { in smu_v13_0_4_get_dpm_ultimate_freq()
796 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_4_get_dpm_ultimate_freq()
827 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_4_get_dpm_ultimate_freq()
850 switch (clk_type) { in smu_v13_0_4_set_soft_freq_limited_range()
897 switch (clk_type) { in smu_v13_0_4_force_clk_levels()
[all …]
A Dyellow_carp_ppt.c731 switch (clk_type) { in yellow_carp_get_current_clk_freq()
765 switch (clk_type) { in yellow_carp_get_dpm_level_count()
798 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index()
837 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled()
908 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in yellow_carp_get_dpm_ultimate_freq()
938 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in yellow_carp_get_dpm_ultimate_freq()
964 switch (clk_type) { in yellow_carp_set_soft_freq_limited_range()
1011 switch (clk_type) { in yellow_carp_get_umd_pstate_clk_default()
1051 switch (clk_type) { in yellow_carp_print_clk_levels()
1127 switch (clk_type) { in yellow_carp_force_clk_levels()
[all …]
A Dsmu_v13_0.c1506 clk_type); in smu_v13_0_get_dpm_ultimate_freq()
1539 enum smu_clk_type clk_type, in smu_v13_0_set_soft_freq_limited_range() argument
1552 clk_type); in smu_v13_0_set_soft_freq_limited_range()
1796 switch (clk_type) { in smu_v13_0_get_boot_freq_by_index()
1839 clk_type); in smu_v13_0_get_dpm_freq_by_index()
1858 enum smu_clk_type clk_type, in smu_v13_0_get_dpm_level_count() argument
1887 clk_type); in smu_v13_0_get_fine_grained_status()
1910 enum smu_clk_type clk_type, in smu_v13_0_set_single_dpm_table() argument
1918 clk_type, in smu_v13_0_set_single_dpm_table()
1927 clk_type, in smu_v13_0_set_single_dpm_table()
[all …]
/drivers/media/platform/qcom/iris/
A Diris_resources.c89 static struct clk *iris_get_clk_by_type(struct iris_core *core, enum platform_clk_type clk_type) in iris_get_clk_by_type() argument
98 if (clk_tbl[i].clk_type == clk_type) { in iris_get_clk_by_type()
109 int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type) in iris_prepare_enable_clock() argument
113 clock = iris_get_clk_by_type(core, clk_type); in iris_prepare_enable_clock()
120 int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type) in iris_disable_unprepare_clock() argument
124 clock = iris_get_clk_by_type(core, clk_type); in iris_disable_unprepare_clock()
A Diris_resources.h15 int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type);
16 int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type);
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c210 switch (clk_type) { in renoir_get_dpm_clk_limited()
290 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
325 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
353 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
510 switch (clk_type) { in renoir_print_clk_levels()
582 switch (clk_type) { in renoir_print_clk_levels()
590 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; in renoir_print_clk_levels()
701 clk_type = clks[i]; in renoir_force_dpm_limit_value()
734 clk_type = clk_feature_map[i].clk_type; in renoir_unforce_dpm_levels()
802 switch (clk_type) { in renoir_force_clk_levels()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c145 enum smu_clk_type clk_type; in smu_set_soft_freq_range() local
154 clk_type, in smu_set_soft_freq_range()
174 clk_type, in smu_get_dpm_freq_range()
522 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { in smu_restore_dpm_user_profile()
3006 clk_type = SMU_ISPICLK; in smu_convert_to_smuclk()
3009 clk_type = SMU_ISPXCLK; in smu_convert_to_smuclk()
3041 return clk_type; in smu_convert_to_smuclk()
3386 clk_type = SMU_GFXCLK; in smu_get_clock_by_type_with_latency()
3389 clk_type = SMU_MCLK; in smu_get_clock_by_type_with_latency()
3392 clk_type = SMU_DCEFCLK; in smu_get_clock_by_type_with_latency()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c527 switch (clk_type) { in vangogh_get_dpm_clk_limited()
580 switch (clk_type) { in vangogh_print_legacy_clk_levels()
635 switch (clk_type) { in vangogh_print_legacy_clk_levels()
682 switch (clk_type) { in vangogh_print_clk_levels()
738 switch (clk_type) { in vangogh_print_clk_levels()
857 switch (clk_type) { in vangogh_clk_dpm_is_enabled()
898 switch (clk_type) { in vangogh_get_dpm_ultimate_freq()
943 switch (clk_type) { in vangogh_get_dpm_ultimate_freq()
1086 switch (clk_type) { in vangogh_set_soft_freq_limited_range()
1168 switch (clk_type) { in vangogh_force_clk_levels()
[all …]
A Dcyan_skillfish_ppt.c260 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
265 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
291 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels() argument
300 switch (clk_type) { in cyan_skillfish_print_clk_levels()
327 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
334 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
536 enum smu_clk_type clk_type, in cyan_skillfish_get_dpm_ultimate_freq() argument
543 switch (clk_type) { in cyan_skillfish_get_dpm_ultimate_freq()
550 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low); in cyan_skillfish_get_dpm_ultimate_freq()
A Dsmu_v11_0.c1064 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1718 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1746 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1770 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1783 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1829 clk_type); in smu_v11_0_set_hard_freq_limited_range()
1992 clk_type); in smu_v11_0_get_dpm_freq_by_index()
2015 enum smu_clk_type clk_type, in smu_v11_0_get_dpm_level_count() argument
2019 clk_type, in smu_v11_0_get_dpm_level_count()
2033 clk_type, in smu_v11_0_set_single_dpm_table()
[all …]
A Dnavi10_ppt.c1184 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument
1192 clk_type); in navi10_get_current_clk_freq_by_table()
1232 clk_type); in navi10_is_support_fine_grained_dpm()
1258 enum smu_clk_type clk_type, in navi10_emit_clk_levels() argument
1277 switch (clk_type) { in navi10_emit_clk_levels()
1302 clk_type, i, &value); in navi10_emit_clk_levels()
1317 clk_type, in navi10_emit_clk_levels()
1488 switch (clk_type) { in navi10_print_clk_levels()
1669 switch (clk_type) { in navi10_force_clk_levels()
1801 enum smu_clk_type clk_type, in navi10_get_clock_by_type_with_latency() argument
[all …]
/drivers/clk/imx/
A Dclk-scu.h34 int num_parents, u32 rsrc_id, u8 clk_type);
38 u32 rsrc_id, u8 clk_type);
52 u8 clk_type) in imx_clk_scu() argument
54 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
58 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
A Dclk-scu.c33 u8 clk_type; member
52 u8 clk_type; member
243 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
316 msg.clk = clk->clk_type; in clk_scu_set_rate()
361 msg.clk = clk->clk_type; in clk_scu_set_parent()
465 clk->clk_type = clk_type; in __imx_clk_scu()
511 if (clk->clk_type == idx) in imx_scu_of_clk_src_get()
541 clk->rsrc, clk->clk_type); in imx_clk_scu_probe()
556 clk->clk_type); in imx_clk_scu_probe()
675 .clk_type = clk_type, in imx_clk_scu_alloc_dev()
[all …]
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c111 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument
120 switch (clk_type) { in get_default_clock_levels()
294 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument
303 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type()
305 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
309 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type()
332 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type()
361 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency() argument
369 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type_with_latency()
381 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_voltage() argument
[all …]
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Dsmu_v11_0.h254 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
257 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
261 enum smu_clk_type clk_type,
272 enum smu_clk_type clk_type,
277 enum smu_clk_type clk_type,
281 enum smu_clk_type clk_type,
A Dsmu_v13_0.h215 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
218 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
228 enum smu_clk_type clk_type,
232 enum smu_clk_type clk_type, uint16_t level,
296 enum smu_clk_type clk_type,
A Dsmu_v14_0.h185 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
188 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
192 enum smu_clk_type clk_type,
203 enum smu_clk_type clk_type,
A Damdgpu_smu.h672 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
685 …int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset…
693 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
716 enum smu_clk_type clk_type,
1269 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u…
1275 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m…
1642 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1645 int smu_set_soft_freq_range(struct smu_context *smu, enum pp_clock_type clk_type,
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.h115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/drivers/phy/
A Dphy-xgene.c706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
1308 xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type); in xgene_phy_hw_init_sata()
[all …]
/drivers/input/
A Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()

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