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Searched refs:clk_values_khz (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/
A Ddcn4_soc_bb.h87 .clk_values_khz = {97000},
91 .clk_values_khz = {300000, 2500000},
95 .clk_values_khz = {200000, 1564000},
99 .clk_values_khz = {100000, 2000000},
103 .clk_values_khz = {100000, 2000000},
107 .clk_values_khz = {100000, 1564000},
111 .clk_values_khz = {810000, 810000},
115 .clk_values_khz = {300000, 1200000},
119 .clk_values_khz = {666667, 666667},
123 .clk_values_khz = {625000, 625000},
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/
A Ddml2_mcg_dcn4.c58 min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
59 min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
139 min_table->dram_bw_table.entries[i].min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[i]; in build_min_clk_table_coarse_grained()
140 min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i]; in build_min_clk_table_coarse_grained()
179 …min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dis… in build_min_clock_table()
180 …min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppcl… in build_min_clock_table()
181 …min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dsccl… in build_min_clock_table()
182 …min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbcl… in build_min_clock_table()
183 …min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phycl… in build_min_clock_table()
189 …min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfcl… in build_min_clock_table()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_translation_helper.c110 dml_clk_table->dcfclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
117 dml_clk_table->dcfclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
133 dml_clk_table->fclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
140 dml_clk_table->fclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
156 dml_clk_table->uclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
163 dml_clk_table->uclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
186 dml_clk_table->dispclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
202 dml_clk_table->dppclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
209 dml_clk_table->dppclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
232 dml_clk_table->dtbclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
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A Ddml21_wrapper.c155 …in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table… in dml21_calculate_rq_and_dlg_params()
157 …max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; in dml21_calculate_rq_and_dlg_params()
162 …in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.… in dml21_calculate_rq_and_dlg_params()
164 …k.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; in dml21_calculate_rq_and_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c268 *rounded_value = clock_table->clk_values_khz[index]; in round_up_and_copy_to_next_dpm()
271 } else if (clock_table->clk_values_khz[clock_table->num_clk_values - 1] >= min_value) { in round_up_and_copy_to_next_dpm()
329 display_cfg->min_clocks.dcn4x.active.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
330 display_cfg->min_clocks.dcn4x.active.uclk_khz <= state_table->uclk.clk_values_khz[index]) { in map_soc_min_clocks_to_dpm_coarse_grained()
332 display_cfg->min_clocks.dcn4x.active.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
333 display_cfg->min_clocks.dcn4x.active.uclk_khz = state_table->uclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
343 display_cfg->min_clocks.dcn4x.idle.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
344 display_cfg->min_clocks.dcn4x.idle.uclk_khz <= state_table->uclk.clk_values_khz[index]) { in map_soc_min_clocks_to_dpm_coarse_grained()
345 display_cfg->min_clocks.dcn4x.idle.dcfclk_khz = state_table->dcfclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
346 display_cfg->min_clocks.dcn4x.idle.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
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/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
A Ddml_top_soc_parameter_types.h108 unsigned long clk_values_khz[DML_MAX_CLK_TABLE_SIZE]; member
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_utils.c539 …L::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk.clk_values_khz[i]); in dml2_core_utils_get_active_min_uclk_dpm_index()
541 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in dml2_core_utils_get_active_min_uclk_dpm_index()
A Ddml2_core_dcn4.c534 if (uclk_freq_khz == soc_bb->clk_table.uclk.clk_values_khz[i]) in lookup_uclk_dpm_index_by_freq()
A Ddml2_core_dcn4_calcs.c7107 …L::%s: clk_table.uclk.clk_values_khz[%d] = %ld\n", __func__, i, clk_table->uclk.clk_values_khz[i]); in get_active_min_uclk_dpm_index()
7109 if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { in get_active_min_uclk_dpm_index()
7940 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml_core_mode_support()
8417 ((double)mode_lib->soc.clk_table.phyclk.clk_values_khz[0] / 1000), in dml_core_mode_support()
8418 ((double)mode_lib->soc.clk_table.phyclk_d18.clk_values_khz[0] / 1000), in dml_core_mode_support()
8419 ((double)mode_lib->soc.clk_table.phyclk_d32.clk_values_khz[0] / 1000), in dml_core_mode_support()
11988 …max_uclk_mhz = mode_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_va… in dml_core_mode_programming()

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