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Searched refs:clkdiv (Results 1 – 25 of 34) sorted by relevance

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/drivers/clk/qcom/
A Dclk-spmi-pmic-div.c25 struct clkdiv { struct
52 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) in is_spmi_pmic_clkdiv_enabled() argument
56 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
62 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, in __spmi_pmic_clkdiv_set_enable_state() argument
69 ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, in __spmi_pmic_clkdiv_set_enable_state()
86 regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); in spmi_pmic_clkdiv_set_enable_state()
94 struct clkdiv *clkdiv = to_clkdiv(hw); in clk_spmi_pmic_div_enable() local
107 struct clkdiv *clkdiv = to_clkdiv(hw); in clk_spmi_pmic_div_disable() local
132 struct clkdiv *clkdiv = to_clkdiv(hw); in clk_spmi_pmic_div_recalc_rate() local
144 struct clkdiv *clkdiv = to_clkdiv(hw); in clk_spmi_pmic_div_set_rate() local
[all …]
/drivers/spi/
A Dspi-cavium.h46 uint64_t clkdiv:13; member
78 uint64_t clkdiv:13;
85 uint64_t clkdiv:13; member
111 uint64_t clkdiv:13;
118 uint64_t clkdiv:13; member
142 uint64_t clkdiv:13;
150 uint64_t clkdiv:13; member
180 uint64_t clkdiv:13;
187 uint64_t clkdiv:13; member
217 uint64_t clkdiv:13;
A Dspi-cavium.c36 unsigned int clkdiv; in octeon_spi_do_transfer() local
48 clkdiv = p->sys_freq / (2 * xfer->speed_hz); in octeon_spi_do_transfer()
52 mpi_cfg.s.clkdiv = clkdiv; in octeon_spi_do_transfer()
A Dspi-pci1xxxx.c139 u8 clkdiv; member
451 u8 clkdiv, u32 len) in pci1xxxx_spi_setup() argument
463 regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv); in pci1xxxx_spi_setup()
489 u8 clkdiv; in pci1xxxx_spi_transfer_with_io() local
493 clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz); in pci1xxxx_spi_transfer_with_io()
517 pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len); in pci1xxxx_spi_transfer_with_io()
562 p->clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz); in pci1xxxx_spi_transfer_with_dma()
570 pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); in pci1xxxx_spi_transfer_with_dma()
675 p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); in pci1xxxx_spi_setup_next_dma_to_io_transfer()
/drivers/hwtracing/intel_th/
A Dpti.c27 unsigned int clkdiv; member
113 return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); in clock_divider_show()
131 pti->clkdiv = val; in clock_divider_store()
159 ctl |= pti->clkdiv << __ffs(PTI_CLKDIV); in intel_th_pti_activate()
183 pti->clkdiv = (ctl & PTI_CLKDIV) >> __ffs(PTI_CLKDIV); in read_hw_config()
188 if (!pti->clkdiv) in read_hw_config()
189 pti->clkdiv = 1; in read_hw_config()
/drivers/w1/masters/
A Dmxc_w1.c95 unsigned int clkdiv; in mxc_w1_probe() local
116 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); in mxc_w1_probe()
117 clkrate /= clkdiv; in mxc_w1_probe()
132 writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER); in mxc_w1_probe()
/drivers/iio/adc/
A Dlpc18xx_adc.c133 unsigned int clkdiv; in lpc18xx_adc_probe() local
176 clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET); in lpc18xx_adc_probe()
178 adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) | in lpc18xx_adc_probe()
/drivers/gpu/drm/exynos/
A Dexynos7_drm_decon.c199 u32 clkdiv; in decon_calc_clkdiv() local
202 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
204 return (clkdiv < 0x100) ? clkdiv : 0xff; in decon_calc_clkdiv()
211 u32 val, clkdiv; in decon_commit() local
260 clkdiv = decon_calc_clkdiv(ctx, mode); in decon_commit()
261 if (clkdiv > 1) { in decon_commit()
262 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); in decon_commit()
A Dexynos_drm_fimd.c195 u32 clkdiv; member
421 u32 clkdiv; in fimd_atomic_check() local
447 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); in fimd_atomic_check()
448 if (clkdiv >= 0x200) { in fimd_atomic_check()
454 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; in fimd_atomic_check()
589 if (ctx->clkdiv > 1) in fimd_commit()
590 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; in fimd_commit()
/drivers/pwm/
A Dpwm-tiehrpwm.c152 unsigned int clkdiv, hspclkdiv; in set_prescale_div() local
154 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { in set_prescale_div()
167 *prescale_div = (1 << clkdiv) * in set_prescale_div()
170 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | in set_prescale_div()
A Dpwm-mediatek.c148 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, in pwm_mediatek_config() local
178 clkdiv++; in pwm_mediatek_config()
183 if (clkdiv > PWM_CLK_DIV_MAX) { in pwm_mediatek_config()
200 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); in pwm_mediatek_config()
/drivers/gpu/drm/tilcdc/
A Dtilcdc_crtc.c208 unsigned int clkdiv; in tilcdc_crtc_set_clk() local
211 clkdiv = 2; /* first try using a standard divider of 2 */ in tilcdc_crtc_set_clk()
216 ret = clk_set_rate(priv->clk, pclk_rate * clkdiv); in tilcdc_crtc_set_clk()
218 real_pclk_rate = clk_rate / clkdiv; in tilcdc_crtc_set_clk()
234 clkdiv = DIV_ROUND_CLOSEST(clk_rate, pclk_rate); in tilcdc_crtc_set_clk()
243 real_pclk_rate = clk_rate / clkdiv; in tilcdc_crtc_set_clk()
255 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv); in tilcdc_crtc_set_clk()
258 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | in tilcdc_crtc_set_clk()
/drivers/mmc/host/
A Dsunplus-mmc.c233 unsigned int clkdiv; in spmmc_set_bus_clk() local
243 clkdiv = (clk_get_rate(host->clk) + clk) / clk - 1; in spmmc_set_bus_clk()
244 if (clkdiv > 0xfff) in spmmc_set_bus_clk()
245 clkdiv = 0xfff; in spmmc_set_bus_clk()
247 value |= FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv); in spmmc_set_bus_clk()
254 int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG)); in spmmc_set_bus_timing() local
255 int delay = clkdiv / 2 < 7 ? clkdiv / 2 : 7; in spmmc_set_bus_timing()
A Dsh_mmcif.c485 unsigned int clkdiv; in sh_mmcif_clock_control() local
497 clkdiv = 0; in sh_mmcif_clock_control()
516 clkdiv = i; in sh_mmcif_clock_control()
522 (best_freq >> (clkdiv + 1)), clk, best_freq, clkdiv); in sh_mmcif_clock_control()
525 clkdiv = clkdiv << 16; in sh_mmcif_clock_control()
527 clkdiv = CLK_SUP_PCLK; in sh_mmcif_clock_control()
529 clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; in sh_mmcif_clock_control()
532 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); in sh_mmcif_clock_control()
A Datmel-mci.c1428 int clkdiv; in atmci_set_ios() local
1451 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2; in atmci_set_ios()
1452 if (clkdiv < 0) { in atmci_set_ios()
1456 clkdiv = 0; in atmci_set_ios()
1457 } else if (clkdiv > 511) { in atmci_set_ios()
1461 clkdiv = 511; in atmci_set_ios()
1463 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) in atmci_set_ios()
1464 | ATMCI_MR_CLKODD(clkdiv & 1); in atmci_set_ios()
1467 if (clkdiv > 255) { in atmci_set_ios()
1471 clkdiv = 255; in atmci_set_ios()
[all …]
A Dsdhci-omap.c701 unsigned long clkdiv; in sdhci_omap_set_clock() local
708 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock); in sdhci_omap_set_clock()
709 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT; in sdhci_omap_set_clock()
710 sdhci_enable_clk(host, clkdiv); in sdhci_omap_set_clock()
/drivers/media/dvb-frontends/
A Dstv6111.c366 u32 clkdiv = 0; in init_state() local
386 if (clkdiv <= 3) in init_state()
387 state->reg[0x00] |= (clkdiv & 0x03); in init_state()
A Dcx24120.c123 u8 clkdiv; member
1116 state->dnxt.clkdiv = (-(rate < 31000001) & 3) + 2; in cx24120_set_symbolrate()
1119 state->dnxt.clkdiv = 3; in cx24120_set_symbolrate()
1191 state->dcur.clkdiv, state->dcur.ratediv); in cx24120_set_frontend()
1218 cmd.arg[13] = state->dcur.clkdiv; in cx24120_set_frontend()
1227 ret = cx24120_writereg(state, CX24120_REG_CLKDIV, state->dcur.clkdiv); in cx24120_set_frontend()
/drivers/gpu/drm/bridge/
A Dtc358775.c380 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay; in tc_bridge_atomic_enable() local
440 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3); in tc_bridge_atomic_enable()
443 t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000; in tc_bridge_atomic_enable()
447 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive; in tc_bridge_atomic_enable()
/drivers/i2c/busses/
A Di2c-ibm_iic.h33 u8 clkdiv; member
A Di2c-ibm_iic.c91 in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt), in dump_iic_regs()
153 out_8(&iic->clkdiv, dev->clckdiv); in iic_dev_init()
/drivers/net/ethernet/
A Dethoc.c1184 u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1); in ethoc_probe() local
1186 if (!clkdiv) in ethoc_probe()
1187 clkdiv = 2; in ethoc_probe()
1188 dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv); in ethoc_probe()
1191 clkdiv); in ethoc_probe()
/drivers/hwmon/
A Dltc4282.c196 u32 clkdiv; in ltc4282_recalc_rate() local
199 ret = regmap_read(st->map, LTC4282_CLK_DIV, &clkdiv); in ltc4282_recalc_rate()
203 clkdiv = FIELD_GET(LTC4282_CLKOUT_MASK, clkdiv); in ltc4282_recalc_rate()
204 if (!clkdiv) in ltc4282_recalc_rate()
206 if (clkdiv == LTC4282_CLKOUT_INT) in ltc4282_recalc_rate()
/drivers/media/pci/netup_unidvb/
A Dnetup_unidvb_i2c.c55 __le16 clkdiv; member
124 writew(TWI_CLKDIV, &i2c->regs->clkdiv); in netup_i2c_reset()
/drivers/net/wireless/broadcom/brcm80211/include/
A Dchipcommon.h79 u32 clkdiv; /* corerev >= 3 */ member

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