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/drivers/net/phy/
A Dmicrochip_rds_ptp.c13 BASE_CLK(clock))); in mchp_rds_phy_read_mmd()
26 BASE_CLK(clock))); in mchp_rds_phy_write_mmd()
210 if (clock->mchp_rds_ptp_event < 0 && pin == clock->event_pin) { in mchp_get_event()
465 if ((type & clock->version) == 0 || (type & clock->layer) == 0) in mchp_rds_ptp_rxtstamp()
1072 return phy_clear_bits_mmd(clock->phydev, PTP_MMD(clock), reg, in mchp_rds_ptp_top_config_intr()
1075 return phy_set_bits_mmd(clock->phydev, PTP_MMD(clock), reg, in mchp_rds_ptp_top_config_intr()
1085 if (!clock) in mchp_rds_ptp_handle_interrupt()
1227 if (!clock) in mchp_rds_ptp_probe()
1259 clock->caps.pin_config = clock->pin_config; in mchp_rds_ptp_probe()
1267 clock->ptp_clock = ptp_clock_register(&clock->caps, in mchp_rds_ptp_probe()
[all …]
A Ddp83640.c542 struct dp83640_clock *clock = dp83640->clock; in enable_status_frames() local
1028 if (clock) in dp83640_clock_get()
1030 return clock; in dp83640_clock_get()
1051 if (clock) in dp83640_clock_get_bus()
1055 if (!clock) in dp83640_clock_get_bus()
1099 struct dp83640_clock *clock = dp83640->clock; in dp83640_config_init() local
1101 if (clock->chosen && !list_empty(&clock->phylist)) in dp83640_config_init()
1424 if (!clock) in dp83640_probe()
1452 dp83640->clock = clock; in dp83640_probe()
1456 clock->ptp_clock = ptp_clock_register(&clock->caps, in dp83640_probe()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Dclock.c358 struct mlx5_clock *clock = mdev->clock; in mlx5_update_clock_info_page() local
384 struct mlx5_clock *clock = mdev->clock; in mlx5_pps_out() local
701 struct mlx5_clock *clock = mdev->clock; in find_target_cycles() local
1002 struct mlx5_clock *clock = mdev->clock; in mlx5_init_pin_config() local
1038 struct mlx5_clock *clock = mdev->clock; in mlx5_get_pps_caps() local
1091 struct mlx5_clock *clock = mdev->clock; in mlx5_pps_event() local
1137 struct mlx5_clock *clock = mdev->clock; in mlx5_timecounter_init() local
1156 struct mlx5_clock *clock = mdev->clock; in mlx5_init_overflow_period() local
1329 clock = &cpriv->clock; in mlx5_clock_alloc()
1331 mdev->clock = clock; in mlx5_clock_alloc()
[all …]
/drivers/net/ethernet/cavium/common/
A Dcavium_ptp.c95 struct cavium_ptp *clock = in cavium_ptp_adjfine() local
142 struct cavium_ptp *clock = in cavium_ptp_adjtime() local
164 struct cavium_ptp *clock = in cavium_ptp_gettime() local
194 timecounter_init(&clock->time_counter, &clock->cycle_counter, nsec); in cavium_ptp_settime()
224 struct cavium_ptp *clock; in cavium_ptp_probe() local
230 clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL); in cavium_ptp_probe()
231 if (!clock) { in cavium_ptp_probe()
236 clock->pdev = pdev; in cavium_ptp_probe()
255 timecounter_init(&clock->time_counter, &clock->cycle_counter, in cavium_ptp_probe()
281 clock->ptp_clock = ptp_clock_register(&clock->ptp_info, dev); in cavium_ptp_probe()
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_dpll.c320 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
321 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
339 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
351 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
352 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
364 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
365 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
597 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
672 if (clock.m2 >= clock.m1) in i9xx_find_best_dpll()
882 clock.p = clock.p1 * clock.p2 * 5; in vlv_find_best_dpll()
[all …]
/drivers/clk/renesas/
A Dclk-div6.c53 writel(val, clock->reg); in cpg_div6_clock_enable()
155 clock->div = div; in cpg_div6_clock_set_rate()
160 writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); in cpg_div6_clock_set_rate()
174 hw_index = (readl(clock->reg) & clock->src_mask) >> in cpg_div6_clock_get_parent()
194 src = clock->parents[index] << __ffs(clock->src_mask); in cpg_div6_clock_set_parent()
195 writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); in cpg_div6_clock_set_parent()
254 clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL); in cpg_div6_register()
255 if (!clock) in cpg_div6_register()
258 clock->reg = reg; in cpg_div6_register()
264 clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; in cpg_div6_register()
[all …]
A DKconfig57 bool "RZ/A1H clock support" if COMPILE_TEST
61 bool "RZ/A2 clock support" if COMPILE_TEST
75 bool "RZ/G1H clock support" if COMPILE_TEST
79 bool "RZ/G1M clock support" if COMPILE_TEST
83 bool "RZ/G1E clock support" if COMPILE_TEST
87 bool "RZ/G1C clock support" if COMPILE_TEST
91 bool "RZ/G2M clock support" if COMPILE_TEST
95 bool "RZ/G2N clock support" if COMPILE_TEST
246 bool "R-Car USB2 clock selector support"
271 bool "MSTP clock support" if COMPILE_TEST
[all …]
/drivers/gpu/drm/gma500/
A Dcdv_intel_display.c395 clock->m = clock->m2 + 2; in cdv_intel_clock()
396 clock->p = clock->p1 * clock->p2; in cdv_intel_clock()
397 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
398 clock->dot = clock->vco / clock->p; in cdv_intel_clock()
409 memset(&clock, 0, sizeof(clock)); in cdv_intel_find_dp_pll()
448 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
661 adjusted_mode->clock, clock.dot); in cdv_intel_crtc_mode_set()
828 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in i8xx_clock()
829 clock->p = clock->p1 * clock->p2; in i8xx_clock()
830 clock->vco = refclk * clock->m / (clock->n + 2); in i8xx_clock()
[all …]
A Doaktrail_crtc.c116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
122 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
123 clock->p1, clock->p2); in mrst_print_pll()
135 memset(&clock, 0, sizeof(clock)); in mrst_sdvo_find_best_pll()
137 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
154 (clock.n * clock.p); in mrst_sdvo_find_best_pll()
192 memset(&clock, 0, sizeof(clock)); in mrst_lvds_find_best_pll()
194 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_lvds_find_best_pll()
512 clock.p1 = (1L << (clock.p1 - 1)); in oaktrail_crtc_mode_set()
514 clock.n = (1L << (clock.n - 1)); in oaktrail_crtc_mode_set()
[all …]
A Dpsb_intel_display.c70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
71 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
72 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
73 clock->dot = clock->vco / clock->p; in psb_intel_clock()
149 &clock); in psb_intel_crtc_mode_set()
152 adjusted_mode->clock, clock.dot); in psb_intel_crtc_mode_set()
156 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
166 adjusted_mode->clock / mode->clock; in psb_intel_crtc_mode_set()
341 clock.p1 = in psb_intel_crtc_clock_get()
345 clock.p2 = 14; in psb_intel_crtc_clock_get()
[all …]
A Dgma_display.c723 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in gma_pll_is_valid()
725 if (clock->p < limit->p.min || limit->p.max < clock->p) in gma_pll_is_valid()
727 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
732 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
734 if (clock->m < limit->m.min || limit->m.max < clock->m) in gma_pll_is_valid()
736 if (clock->n < limit->n.min || limit->n.max < clock->n) in gma_pll_is_valid()
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in gma_find_best_pll()
785 (clock.m2 < clock.m1 || clock.m1 == 0) && in gma_find_best_pll()
786 clock.m2 <= limit->m2.max; clock.m2++) { in gma_find_best_pll()
788 clock.n <= limit->n.max; clock.n++) { in gma_find_best_pll()
[all …]
/drivers/soc/fsl/qe/
A Ducc.c139 switch (clock) { in ucc_set_qe_mux_rxtx()
154 switch (clock) { in ucc_set_qe_mux_rxtx()
169 switch (clock) { in ucc_set_qe_mux_rxtx()
185 switch (clock) { in ucc_set_qe_mux_rxtx()
231 switch (clock) { in ucc_get_tdm_common_clk()
252 switch (clock) { in ucc_get_tdm_common_clk()
282 switch (clock) { in ucc_get_tdm_rx_clk()
294 switch (clock) { in ucc_get_tdm_rx_clk()
306 switch (clock) { in ucc_get_tdm_rx_clk()
318 switch (clock) { in ucc_get_tdm_rx_clk()
[all …]
/drivers/video/fbdev/via/
A Dvia_clock.c289 clock->set_primary_pll_state = dummy_set_pll_state; in via_clock_init()
290 clock->set_primary_pll = cle266_set_primary_pll; in via_clock_init()
297 clock->set_engine_pll_state = dummy_set_pll_state; in via_clock_init()
298 clock->set_engine_pll = dummy_set_pll; in via_clock_init()
312 clock->set_primary_pll = k800_set_primary_pll; in via_clock_init()
317 clock->set_secondary_pll = k800_set_secondary_pll; in via_clock_init()
319 clock->set_engine_pll_state = set_engine_pll_state; in via_clock_init()
320 clock->set_engine_pll = k800_set_engine_pll; in via_clock_init()
327 clock->set_primary_pll = vx855_set_primary_pll; in via_clock_init()
332 clock->set_secondary_pll = vx855_set_secondary_pll; in via_clock_init()
[all …]
/drivers/clk/sophgo/
A DKconfig2 # common clock support for SOPHGO SoC family.
10 It includes PLLs, common clock function and some vendor clock for
14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
29 This driver provides clock function such as DIV/Mux/Gate.
38 clock from Clock Generator IP as input.
42 tristate "Sophgo SG2044 clock controller support"
47 This clock control provides PLL clocks and common clock function
51 tristate "Sophgo SG2044 PLL clock controller support"
[all …]
/drivers/net/ethernet/mellanox/mlxsw/
A Dspectrum_ptp.c243 timecounter_init(&clock->tc, &clock->cycles, nsec); in mlxsw_sp1_ptp_settime()
280 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in mlxsw_sp1_ptp_clock_init()
281 if (!clock) in mlxsw_sp1_ptp_clock_init()
289 clock->nominal_c_mult = clock->cycles.mult; in mlxsw_sp1_ptp_clock_init()
293 timecounter_init(&clock->tc, &clock->cycles, 0); in mlxsw_sp1_ptp_clock_init()
323 kfree(clock); in mlxsw_sp1_ptp_clock_init()
334 kfree(clock); in mlxsw_sp1_ptp_clock_fini()
449 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in mlxsw_sp2_ptp_clock_init()
450 if (!clock) in mlxsw_sp2_ptp_clock_init()
463 clock->ptp = ptp_clock_register(&clock->ptp_info, dev); in mlxsw_sp2_ptp_clock_init()
[all …]
/drivers/clk/bcm/
A DKconfig15 bool "Broadcom BCM2835 clock support"
24 bool "Broadcom BCM63xx clock support"
33 bool "Broadcom BCM63xx gated clock support"
41 bool "Broadcom BCM63268 timer clock and reset support"
50 bool "Broadcom Kona CCU clock support"
65 bool "Broadcom Cygnus clock support"
73 bool "Broadcom Hurricane 2 clock support"
82 bool "Broadcom Northstar/Northstar Plus clock support"
91 bool "Broadcom Northstar 2 clock support"
99 bool "Broadcom Stingray clock support"
[all …]
/drivers/clk/
A Dkunit_clk_parent_data_test.dtso8 fixed_50: kunit-clock-50MHz {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <50000000>;
12 clock-output-names = CLK_PARENT_DATA_50MHZ_NAME;
15 fixed_parent: kunit-clock-1MHz {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <1000000>;
22 kunit-clock-controller {
[all …]
/drivers/media/platform/qcom/camss/
A Dcamss.c121 .clock = { "top_ahb", "ahb", "ispif_ahb",
133 .clock = { "top_ahb", "vfe0", "csi_vfe0",
230 .clock = { "top_ahb", "ahb", "ispif_ahb",
753 .clock = { "soc_ahb", "cpas_ahb",
771 .clock = { "soc_ahb", "cpas_ahb",
789 .clock = { "soc_ahb", "cpas_ahb",
2280 .clock = { "csid", "csiphy_rx" },
2295 .clock = { "csid", "csiphy_rx" },
2310 .clock = { "csid", "csiphy_rx" },
2818 clk_disable_unprepare(clock[i].clk); in camss_enable_clocks()
[all …]
/drivers/ptp/
A DKconfig3 # PTP clock support configuration
6 menu "PTP clock support"
9 tristate "PTP clock support"
65 timer as a PTP clock. This clock is only useful if your PTP
85 clock. This clock is only useful if your PTP programs are
129 clock. This clock is only useful if you are using KVM guests.
157 clock. This clock is only useful if your time stamping MAC
169 clock. This clock is only useful if your time stamping MAC
181 as a PTP clock. This clock is only useful if your time stamping
204 clock device as a PTP clock. This is only useful in virtual
[all …]
A Dptp_ines.c186 port = &clock->port[i]; in ines_clock_cleanup()
200 clock->node = node; in ines_clock_init()
201 clock->dev = device; in ines_clock_init()
202 clock->base = addr; in ines_clock_init()
203 clock->regs = clock->base; in ines_clock_init()
210 port->clock = clock; in ines_clock_init()
740 clock = kzalloc(sizeof(*clock), GFP_KERNEL); in ines_ptp_ctrl_probe()
741 if (!clock) { in ines_ptp_ctrl_probe()
746 kfree(clock); in ines_ptp_ctrl_probe()
752 kfree(clock); in ines_ptp_ctrl_probe()
[all …]
/drivers/clk/samsung/
A DKconfig4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
42 Support for the clock controller present on the Samsung
50 Support for the clock controller present on the Samsung
57 Support for the clock controller present on the Samsung
64 Support for the clock controller present on the Samsung
71 Support for the clock controller present on the Samsung
80 tristate "Samsung Exynos AUDSS clock controller support"
89 tristate "Samsung Exynos clock output driver"
96 other devices as an input clock.
[all …]
/drivers/clk/ti/
A Dadpll.c244 struct clk *clock; in ti_adpll_init_divider() local
254 if (IS_ERR(clock)) { in ti_adpll_init_divider()
273 struct clk *clock; in ti_adpll_init_mux() local
282 if (IS_ERR(clock)) { in ti_adpll_init_mux()
302 struct clk *clock; in ti_adpll_init_gate() local
331 struct clk *clock; in ti_adpll_init_fixed_factor() local
340 if (IS_ERR(clock)) in ti_adpll_init_fixed_factor()
487 struct clk *clock; in ti_adpll_init_dco() local
527 if (IS_ERR(clock)) in ti_adpll_init_dco()
583 struct clk *clock; in ti_adpll_init_clkout() local
[all …]
/drivers/clk/rockchip/
A DKconfig2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
13 bool "Rockchip PX30 clock controller support"
20 bool "Rockchip RV110x clock controller support"
27 bool "Rockchip RV1126 clock controller support"
34 bool "Rockchip RK3036 clock controller support"
41 bool "Rockchip RK312x clock controller support"
48 bool "Rockchip RK3188 clock controller support"
55 bool "Rockchip RK322x clock controller support"
62 bool "Rockchip RK3288 clock controller support"
[all …]
/drivers/clk/starfive/
A DKconfig7 bool "StarFive JH7100 clock support"
16 tristate "StarFive JH7100 audio clock support"
25 bool "StarFive JH7110 PLL clock support"
29 Say yes here to support the PLL clock controller on the
33 bool "StarFive JH7110 system clock support"
41 Say yes here to support the system clock controller on the
45 tristate "StarFive JH7110 always-on clock support"
53 tristate "StarFive JH7110 System-Top-Group clock support"
61 tristate "StarFive JH7110 Image-Signal-Process clock support"
69 tristate "StarFive JH7110 Video-Output clock support"
[all …]
/drivers/clk/qcom/
A DKconfig11 tristate "Support for Qualcomm's clock controllers"
27 Support for the camera clock controller on X1E80100 devices.
35 Support for the two display clock controllers on Qualcomm
186 clock that feeds the CPUs on ipq based devices.
298 PHY device. Select this for the root clock of qca8k.
552 tristate "QCS615 Graphics clock controller"
657 tristate "SA8775P Graphics clock controller"
675 tristate "SAR2130P Graphics clock controller"
776 core clock controller.
787 core clock controller.
[all …]

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