Searched refs:clock_lane (Results 1 – 8 of 8) sorted by relevance
133 u32 clock_lane = 0; in v4l2_fwnode_endpoint_parse_csi2_bus() local147 clock_lane = bus->clock_lane; in v4l2_fwnode_endpoint_parse_csi2_bus()148 if (clock_lane) in v4l2_fwnode_endpoint_parse_csi2_bus()212 clock_lane = v; in v4l2_fwnode_endpoint_parse_csi2_bus()217 if (have_clk_lane && lanes_used & BIT(clock_lane) && in v4l2_fwnode_endpoint_parse_csi2_bus()242 bus->clock_lane = 0; in v4l2_fwnode_endpoint_parse_csi2_bus()246 bus->clock_lane = clock_lane; in v4l2_fwnode_endpoint_parse_csi2_bus()451 bus->clock_lane = v; in v4l2_fwnode_endpoint_parse_csi1_bus()
107 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); in cal_camerarx_lane_config()620 endpoint->bus.mipi_csi2.clock_lane, data_lanes, in cal_camerarx_parse_dt()
337 if (ep->bus.mipi_csi2.clock_lane != 0) { in mipid02_configure_clk_lane()
1171 if (ep.bus.mipi_csi2.clock_lane != 0) { in vd56g3_check_csi_conf()
1674 if (ep.bus.mipi_csi2.clock_lane != 0) { in vd55g1_check_csi_conf()
1444 log2phy[0] = ep.bus.mipi_csi2.clock_lane; in vgxy61_tx_from_ep()
2056 buscfg->bus.csi2.lanecfg.clk.pos = vep->bus.mipi_csi2.clock_lane; in isp_parse_of_csi2_endpoint()2086 buscfg->bus.ccp2.lanecfg.clk.pos = vep->bus.mipi_csi1.clock_lane; in isp_parse_of_csi1_endpoint()
3009 lncfg->clk.pos = mipi_csi2->clock_lane; in camss_of_parse_endpoint_node()
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