| /drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| A D | dcn303_fpu.c | 113 .clock_limits = {
230 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
325 dcn3_03_soc.clock_limits[i].state = i; in dcn303_fpu_update_bw_bounding_box()
326 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn303_fpu_update_bw_bounding_box()
336 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz; in dcn303_fpu_update_bw_bounding_box()
340 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz; in dcn303_fpu_update_bw_bounding_box()
345 dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz; in dcn303_fpu_update_bw_bounding_box()
346 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; in dcn303_fpu_update_bw_bounding_box()
351 if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700) in dcn303_fpu_update_bw_bounding_box()
355 dcn3_03_soc.clock_limits[i].dcfclk_mhz = 100; in dcn303_fpu_update_bw_bounding_box()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | dcn314_fpu.c | 103 .clock_limits = {
186 dcn3_14_soc.clock_limits; in dcn314_update_bw_bounding_box_fpu()
228 clock_limits[i].state = i; in dcn314_update_bw_bounding_box_fpu()
233 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
235 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn314_update_bw_bounding_box_fpu()
250 …clock_limits[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan… in dcn314_update_bw_bounding_box_fpu()
251 clock_limits[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn314_update_bw_bounding_box_fpu()
252 clock_limits[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn314_update_bw_bounding_box_fpu()
253 clock_limits[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; in dcn314_update_bw_bounding_box_fpu()
254 clock_limits[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn314_update_bw_bounding_box_fpu()
[all …]
|
| A D | display_mode_vba_314.c | 2138 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| A D | dcn351_fpu.c | 98 .clock_limits = {
303 clock_limits[i].state = i; in dcn351_update_bw_bounding_box_fpu()
308 clock_limits[i].dcfclk_mhz < in dcn351_update_bw_bounding_box_fpu()
311 clock_limits[i].dcfclk_mhz = in dcn351_update_bw_bounding_box_fpu()
317 clock_limits[i].socclk_mhz = in dcn351_update_bw_bounding_box_fpu()
337 clock_limits[i].dscclk_mhz = in dcn351_update_bw_bounding_box_fpu()
339 clock_limits[i].dtbclk_mhz = in dcn351_update_bw_bounding_box_fpu()
343 clock_limits[i].phyclk_mhz = in dcn351_update_bw_bounding_box_fpu()
347 memcpy(dcn3_51_soc.clock_limits, clock_limits, in dcn351_update_bw_bounding_box_fpu()
393 clock_limits[i].dcfclk_mhz; in dcn351_update_bw_bounding_box_fpu()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| A D | dcn35_fpu.c | 119 .clock_limits = {
269 clock_limits[i].state = i; in dcn35_update_bw_bounding_box_fpu()
274 clock_limits[i].dcfclk_mhz < in dcn35_update_bw_bounding_box_fpu()
277 clock_limits[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()
283 clock_limits[i].socclk_mhz = in dcn35_update_bw_bounding_box_fpu()
303 clock_limits[i].dscclk_mhz = in dcn35_update_bw_bounding_box_fpu()
305 clock_limits[i].dtbclk_mhz = in dcn35_update_bw_bounding_box_fpu()
309 clock_limits[i].phyclk_mhz = in dcn35_update_bw_bounding_box_fpu()
313 memcpy(dcn3_5_soc.clock_limits, clock_limits, in dcn35_update_bw_bounding_box_fpu()
359 clock_limits[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| A D | dcn302_fpu.c | 114 .clock_limits = {
234 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
238 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
240 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
319 dcn3_02_soc.clock_limits[i].state = i; in dcn302_fpu_update_bw_bounding_box()
320 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn302_fpu_update_bw_bounding_box()
326 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
330 dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz; in dcn302_fpu_update_bw_bounding_box()
334 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz; in dcn302_fpu_update_bw_bounding_box()
339 dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz; in dcn302_fpu_update_bw_bounding_box()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 122 .clock_limits = {
366 .clock_limits = {
600 memcpy(s, dcn3_1_soc.clock_limits, sizeof(dcn3_1_soc.clock_limits)); in dcn31_update_bw_bounding_box()
637 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn31_update_bw_bounding_box()
640 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn31_update_bw_bounding_box()
654 memcpy(dcn3_1_soc.clock_limits, s, sizeof(dcn3_1_soc.clock_limits)); in dcn31_update_bw_bounding_box()
694 dcn3_15_soc.clock_limits[i].state = i; in dcn315_update_bw_bounding_box()
739 memcpy(s, dcn3_16_soc.clock_limits, sizeof(dcn3_16_soc.clock_limits)); in dcn316_update_bw_bounding_box()
777 dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn316_update_bw_bounding_box()
780 dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn316_update_bw_bounding_box()
[all …]
|
| A D | display_mode_vba_31.c | 2120 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 113 .clock_limits = {
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
333 memcpy(s, dcn3_01_soc.clock_limits, sizeof(dcn3_01_soc.clock_limits)); in dcn301_fpu_update_bw_bounding_box()
357 s[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_fpu_update_bw_bounding_box()
359 dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; in dcn301_fpu_update_bw_bounding_box()
360 s[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn301_fpu_update_bw_bounding_box()
361 s[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn301_fpu_update_bw_bounding_box()
363 dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; in dcn301_fpu_update_bw_bounding_box()
371 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; in dcn301_fpu_update_bw_bounding_box()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 223 .clock_limits = {
334 .clock_limits = {
445 .clock_limits = {
626 .clock_limits = {
1863 memset(bb->clock_limits, 0, sizeof(bb->clock_limits)); in dcn20_update_bounding_box()
1960 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) in dcn20_cap_soc_clocks()
1964 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) in dcn20_cap_soc_clocks()
1968 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) in dcn20_cap_soc_clocks()
1972 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) in dcn20_cap_soc_clocks()
2418 memcpy(s, dcn2_1_soc.clock_limits, sizeof(dcn2_1_soc.clock_limits)); in dcn21_update_bw_bounding_box()
[all …]
|
| A D | display_mode_vba_20.c | 1257 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
|
| A D | display_mode_vba_20v2.c | 1317 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| A D | dcn321_fpu.c | 106 .clock_limits = {
732 max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu()
736 max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; in dcn321_update_bw_bounding_box_fpu()
818 dcn3_21_soc.clock_limits[i].state = i; in dcn321_update_bw_bounding_box_fpu()
819 dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn321_update_bw_bounding_box_fpu()
831 dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; in dcn321_update_bw_bounding_box_fpu()
840 dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; in dcn321_update_bw_bounding_box_fpu()
845 dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; in dcn321_update_bw_bounding_box_fpu()
851 dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; in dcn321_update_bw_bounding_box_fpu()
852 dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; in dcn321_update_bw_bounding_box_fpu()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 126 .clock_limits = {
504 if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { in dcn30_fpu_calculate_wm_and_dlg()
535 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_update_max_clk()
582 dcn3_0_soc.clock_limits[i].state = i; in dcn30_fpu_update_bw_bounding_box()
583 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box()
584 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn30_fpu_update_bw_bounding_box()
585 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; in dcn30_fpu_update_bw_bounding_box()
591 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; in dcn30_fpu_update_bw_bounding_box()
594 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz; in dcn30_fpu_update_bw_bounding_box()
595 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz; in dcn30_fpu_update_bw_bounding_box()
[all …]
|
| A D | display_mode_vba_30.c | 1979 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 127 .clock_limits = {
2308 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2431 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
3268 dcn3_2_soc.clock_limits[i].state = i; in dcn32_update_bw_bounding_box_fpu()
3281 dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; in dcn32_update_bw_bounding_box_fpu()
3290 dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; in dcn32_update_bw_bounding_box_fpu()
3295 dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; in dcn32_update_bw_bounding_box_fpu()
3301 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; in dcn32_update_bw_bounding_box_fpu()
3302 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; in dcn32_update_bw_bounding_box_fpu()
3306 dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states); in dcn32_update_bw_bounding_box_fpu()
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.c | 377 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()
380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
383 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()
395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
397 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
401 mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz; in fetch_socbb_params()
402 mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz; in fetch_socbb_params()
[all …]
|
| A D | display_mode_structs.h | 182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
|
| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 719 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz; in dml2_translate_soc_states()
720 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; in dml2_translate_soc_states()
721 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; in dml2_translate_soc_states()
722 out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts; in dml2_translate_soc_states()
723 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz; in dml2_translate_soc_states()
724 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz; in dml2_translate_soc_states()
725 out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz; in dml2_translate_soc_states()
726 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; in dml2_translate_soc_states()
727 out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz; in dml2_translate_soc_states()
728 out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz; in dml2_translate_soc_states()
[all …]
|
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_socbb.h | 79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 139 .clock_limits = {
|
| /drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 1724 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
|
| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 1641 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
|