Searched refs:clock_names (Results 1 – 7 of 7) sorted by relevance
| /drivers/reset/ |
| A D | reset-uniphier-glue.c | 19 const char * const *clock_names; member
59 priv->clk[i].id = priv->data->clock_names[i]; in uniphier_glue_reset_probe()
96 .clock_names = uniphier_pro4_clock_reset_names,
107 .clock_names = uniphier_pxs2_clock_reset_names,
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| /drivers/regulator/ |
| A D | uniphier-regulator.c | 22 const char * const *clock_names; member
65 priv->clk[i].id = priv->data->clock_names[i]; in uniphier_regulator_probe()
158 .clock_names = uniphier_pro4_clock_reset_names,
171 .clock_names = uniphier_pxs2_clock_reset_names,
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| /drivers/net/ethernet/socionext/ |
| A D | sni_ave.c | 291 const char *clock_names[AVE_MAX_CLKS]; member
1643 name = priv->data->clock_names[i]; in ave_probe()
1882 .clock_names = {
1893 .clock_names = {
1904 .clock_names = {
1915 .clock_names = {
1926 .clock_names = {
1937 .clock_names = {
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| /drivers/bus/ |
| A D | ti-sysc.c | 98 static const char * const clock_names[SYSC_MAX_CLOCKS] = { variable
383 optfck_name = clock_names[index]; in sysc_init_ext_opt_clock()
399 if (!strncmp(clock_names[SYSC_FCK], name, 3)) in sysc_get_one_clock()
401 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) in sysc_get_one_clock()
452 if (!strncmp(clock_names[SYSC_FCK], name, 3)) in sysc_get_clocks()
454 if (!strncmp(clock_names[SYSC_ICK], name, 3)) in sysc_get_clocks()
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| /drivers/net/can/rcar/ |
| A D | rcar_can.c | 733 static const char * const clock_names[] = { variable
785 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); in rcar_can_probe()
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| /drivers/iio/ |
| A D | industrialio-core.c | 1448 static const char * const clock_names[] = { variable
1483 return sysfs_emit(buf, "%s\n", clock_names[clk]); in current_timestamp_clock_show()
1493 ret = sysfs_match_string(clock_names, buf); in current_timestamp_clock_store()
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| /drivers/usb/gadget/udc/ |
| A D | tegra-xudc.c | 547 const char * const *clock_names; member
3642 .clock_names = tegra210_xudc_clock_names,
3656 .clock_names = tegra186_xudc_clock_names,
3670 .clock_names = tegra186_xudc_clock_names,
3684 .clock_names = tegra186_xudc_clock_names,
3819 xudc->clks[i].id = xudc->soc->clock_names[i]; in tegra_xudc_probe()
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