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Searched refs:clock_table (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c484 const DpmClocks_315_t *clock_table) in dcn315_clk_mgr_helper_populate_bw_params() argument
488 uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1; in dcn315_clk_mgr_helper_populate_bw_params()
492 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) { in dcn315_clk_mgr_helper_populate_bw_params()
496 for (j = clock_table->NumDfPstatesEnabled - 2; j >= 0; j--) { in dcn315_clk_mgr_helper_populate_bw_params()
497 if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]) in dcn315_clk_mgr_helper_populate_bw_params()
501 if (i == clock_table->NumDcfClkLevelsEnabled - 1) in dcn315_clk_mgr_helper_populate_bw_params()
531 } else if (clock_table->NumDcfClkLevelsEnabled != clock_table->NumSocClkLevelsEnabled) { in dcn315_clk_mgr_helper_populate_bw_params()
532 …bw_params->clk_table.entries[i-1].voltage = clock_table->SocVoltage[clock_table->NumSocClkLevelsEn… in dcn315_clk_mgr_helper_populate_bw_params()
533 …bw_params->clk_table.entries[i-1].socclk_mhz = clock_table->SocClocks[clock_table->NumSocClkLevels… in dcn315_clk_mgr_helper_populate_bw_params()
534 …bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLev… in dcn315_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.c619 const DpmClocks314_t *clock_table) in dcn314_clk_mgr_helper_populate_bw_params() argument
629 clock_table->DfPstateTable[i].FClk > max_fclk) { in dcn314_clk_mgr_helper_populate_bw_params()
630 max_fclk = clock_table->DfPstateTable[i].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
641 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
642 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
655 clock_table->DfPstateTable[j].FClk < min_fclk && in dcn314_clk_mgr_helper_populate_bw_params()
656 clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]) { in dcn314_clk_mgr_helper_populate_bw_params()
657 min_fclk = clock_table->DfPstateTable[j].FClk; in dcn314_clk_mgr_helper_populate_bw_params()
680 clock_table->DfPstateTable[min_pstate].WckRatio); in dcn314_clk_mgr_helper_populate_bw_params()
696 clock_table->DfPstateTable[max_pstate].WckRatio); in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c460 const DpmClocks_316_t *clock_table, in find_clk_for_voltage() argument
469 if (clock_table->SocVoltage[i] == voltage) { in find_clk_for_voltage()
472 clock_table->SocVoltage[i] < voltage) { in find_clk_for_voltage()
473 max_voltage = clock_table->SocVoltage[i]; in find_clk_for_voltage()
485 const DpmClocks_316_t *clock_table) in dcn316_clk_mgr_helper_populate_bw_params() argument
499 if (clock_table->DfPstateTable[i].FClk != 0) { in dcn316_clk_mgr_helper_populate_bw_params()
516 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
517 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
528 switch (clock_table->DfPstateTable[j].WckRatio) { in dcn316_clk_mgr_helper_populate_bw_params()
538 …temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Vol… in dcn316_clk_mgr_helper_populate_bw_params()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c903 DpmClocks_t_dcn35 *clock_table) in dcn35_clk_mgr_helper_populate_bw_params() argument
914 clock_table->NumMemPstatesEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
937 ASSERT(clock_table->NumMemPstatesEnabled && in dcn35_clk_mgr_helper_populate_bw_params()
945 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()
946 max_dppclk = find_max_clk_value(clock_table->DppClocks, in dcn35_clk_mgr_helper_populate_bw_params()
947 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()
954 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0); in dcn35_clk_mgr_helper_populate_bw_params()
957 clock_table->NumFclkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
961 clock_table->NumDcfClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1003 clock_table->MemPstateTable[max_pstate].WckRatio); in dcn35_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c534 const DpmClocks_t *clock_table, in find_clk_for_voltage() argument
543 if (clock_table->SocVoltage[i] == voltage) { in find_clk_for_voltage()
546 clock_table->SocVoltage[i] < voltage) { in find_clk_for_voltage()
547 max_voltage = clock_table->SocVoltage[i]; in find_clk_for_voltage()
558 const DpmClocks_t *clock_table) in dcn31_clk_mgr_helper_populate_bw_params() argument
572 if (clock_table->DfPstateTable[i].FClk != 0) { in dcn31_clk_mgr_helper_populate_bw_params()
589 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
590 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
599 switch (clock_table->DfPstateTable[j].WckRatio) { in dcn31_clk_mgr_helper_populate_bw_params()
609 …_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_tab… in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c619 if (clock_table->SocClocks[i].Vol == voltage) in find_socclk_for_voltage()
620 return clock_table->SocClocks[i].Freq; in find_socclk_for_voltage()
632 if (clock_table->DcfClocks[i].Vol == voltage) in find_dcfclk_for_voltage()
633 return clock_table->DcfClocks[i].Freq; in find_dcfclk_for_voltage()
652 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) { in rn_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
668 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
669 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
670 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
671 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, in rn_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c543 static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table, in find_dcfclk_for_voltage() argument
551 if (clock_table->SocVoltage[i] == voltage) in find_dcfclk_for_voltage()
552 return clock_table->DcfClocks[i]; in find_dcfclk_for_voltage()
562 const struct vg_dpm_clocks *clock_table) in vg_clk_mgr_helper_populate_bw_params() argument
575 if (clock_table->DfPstateTable[i].fclk != 0) { in vg_clk_mgr_helper_populate_bw_params()
590 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
592 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; in vg_clk_mgr_helper_populate_bw_params()
593 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params()
595 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
596 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
[all …]
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu8_hwmgr.c437 struct SMU8_Fusion_ClkTable *clock_table; in smu8_upload_pptable_to_smu() local
462 clock_table = (struct SMU8_Fusion_ClkTable *)table; in smu8_upload_pptable_to_smu()
479 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid = in smu8_upload_pptable_to_smu()
488 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid = in smu8_upload_pptable_to_smu()
492 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid = in smu8_upload_pptable_to_smu()
496 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid = in smu8_upload_pptable_to_smu()
505 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid = in smu8_upload_pptable_to_smu()
510 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid = in smu8_upload_pptable_to_smu()
519 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid = in smu8_upload_pptable_to_smu()
522 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid = in smu8_upload_pptable_to_smu()
[all …]
A Dsmu10_hwmgr.c499 DpmClocks_t *table = &(smu10_data->clock_table); in smu10_populate_clock_table()
511 &smu10_data->clock_table.DcefClocks[0]); in smu10_populate_clock_table()
514 &smu10_data->clock_table.SocClocks[0]); in smu10_populate_clock_table()
517 &smu10_data->clock_table.FClocks[0]); in smu10_populate_clock_table()
520 &smu10_data->clock_table.MemClocks[0]); in smu10_populate_clock_table()
643 if (min_mclk < data->clock_table.FClocks[0].Freq) in smu10_dpm_force_dpm_level()
644 min_mclk = data->clock_table.FClocks[0].Freq; in smu10_dpm_force_dpm_level()
A Dprocesspptables.c410 struct phm_clock_array *clock_table; in get_valid_clk() local
412 clock_table = kzalloc(struct_size(clock_table, values, table->count), GFP_KERNEL); in get_valid_clk()
413 if (!clock_table) in get_valid_clk()
416 clock_table->count = (unsigned long)table->count; in get_valid_clk()
418 for (i = 0; i < clock_table->count; i++) in get_valid_clk()
419 clock_table->values[i] = (unsigned long)table->entries[i].clk; in get_valid_clk()
421 *ptable = clock_table; in get_valid_clk()
A Dsmu10_hwmgr.h297 DpmClocks_t clock_table; member
/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Drenoir_ppt.c756 if (!clock_table || !table) in renoir_get_dpm_clock_table()
760 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq; in renoir_get_dpm_clock_table()
761 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol; in renoir_get_dpm_clock_table()
766 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol; in renoir_get_dpm_clock_table()
770 clock_table->FClocks[i].Freq = table->FClocks[i].Freq; in renoir_get_dpm_clock_table()
771 clock_table->FClocks[i].Vol = table->FClocks[i].Vol; in renoir_get_dpm_clock_table()
776 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol; in renoir_get_dpm_clock_table()
780 clock_table->VClocks[i].Freq = table->VClocks[i].Freq; in renoir_get_dpm_clock_table()
781 clock_table->VClocks[i].Vol = table->VClocks[i].Vol; in renoir_get_dpm_clock_table()
785 clock_table->DClocks[i].Freq = table->DClocks[i].Freq; in renoir_get_dpm_clock_table()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c1568 static int smu_14_0_1_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) in smu_14_0_1_get_dpm_table() argument
1576 clock_table->SocClocks[idx].Vol = 0; in smu_14_0_1_get_dpm_table()
1580 …clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[i… in smu_14_0_1_get_dpm_table()
1581 clock_table->VPEClocks[idx].Vol = 0; in smu_14_0_1_get_dpm_table()
1587 static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) in smu_14_0_0_get_dpm_table() argument
1595 clock_table->SocClocks[idx].Vol = 0; in smu_14_0_0_get_dpm_table()
1599 …clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[i… in smu_14_0_0_get_dpm_table()
1600 clock_table->VPEClocks[idx].Vol = 0; in smu_14_0_0_get_dpm_table()
1606 static int smu_v14_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) in smu_v14_0_common_get_dpm_table() argument
1609 smu_14_0_1_get_dpm_table(smu, clock_table); in smu_v14_0_common_get_dpm_table()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c258 …pm(unsigned long min_value, unsigned long *rounded_value, const struct dml2_clk_table *clock_table) in round_up_and_copy_to_next_dpm() argument
263 if (clock_table->num_clk_values > 2) { in round_up_and_copy_to_next_dpm()
264 while (index < clock_table->num_clk_values && clock_table->clk_values_khz[index] < min_value) in round_up_and_copy_to_next_dpm()
267 if (index < clock_table->num_clk_values) { in round_up_and_copy_to_next_dpm()
268 *rounded_value = clock_table->clk_values_khz[index]; in round_up_and_copy_to_next_dpm()
271 } else if (clock_table->clk_values_khz[clock_table->num_clk_values - 1] >= min_value) { in round_up_and_copy_to_next_dpm()
278 …tic bool round_up_to_next_dpm(unsigned long *clock_value, const struct dml2_clk_table *clock_table) in round_up_to_next_dpm() argument
280 return round_up_and_copy_to_next_dpm(*clock_value, clock_value, clock_table); in round_up_to_next_dpm()
/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h286 struct dpm_clocks *clock_table);
306 struct dpm_clocks *clock_table);
/drivers/tty/serial/8250/
A D8250_fintek.c293 static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ, in fintek_8250_set_termios() local
335 clock_table[i]); in fintek_8250_set_termios()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_vpe.c127 struct dpm_clocks clock_table = { 0 }; in amdgpu_vpe_configure_dpm() local
140 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) { in amdgpu_vpe_configure_dpm()
145 SOCClks = clock_table.SocClocks; in amdgpu_vpe_configure_dpm()
146 VPEClks = clock_table.VPEClocks; in amdgpu_vpe_configure_dpm()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dvangogh_ppt.c2171 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table) in vangogh_get_dpm_clock_table() argument
2176 if (!clock_table || !table) in vangogh_get_dpm_clock_table()
2180 clock_table->SocClocks[i].Freq = table->SocClocks[i]; in vangogh_get_dpm_clock_table()
2181 clock_table->SocClocks[i].Vol = table->SocVoltage[i]; in vangogh_get_dpm_clock_table()
2185 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk; in vangogh_get_dpm_clock_table()
2186 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage; in vangogh_get_dpm_clock_table()
2190 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk; in vangogh_get_dpm_clock_table()
2191 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage; in vangogh_get_dpm_clock_table()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c727 struct pp_smu *pp, struct dpm_clocks *clock_table) in pp_rn_get_dpm_clock_table() argument
733 ret = amdgpu_dpm_get_dpm_clock_table(adev, clock_table); in pp_rn_get_dpm_clock_table()
/drivers/usb/serial/
A Df81232.c128 static u8 const clock_table[] = { F81232_CLK_1_846_MHZ, F81232_CLK_14_77_MHZ, variable
520 F81232_CLK_MASK, clock_table[idx]); in f81232_set_baudrate()
A Df81534.c190 static u8 const clock_table[] = { F81534_CLK_1_846_MHZ, F81534_CLK_14_77_MHZ, variable
586 port_priv->shadow_clk |= clock_table[idx]; in f81534_set_port_config()
/drivers/gpu/drm/amd/pm/inc/
A Damdgpu_dpm.h608 struct dpm_clocks *clock_table);
/drivers/gpu/drm/amd/pm/
A Damdgpu_dpm.c2024 struct dpm_clocks *clock_table) in amdgpu_dpm_get_dpm_clock_table() argument
2034 clock_table); in amdgpu_dpm_get_dpm_clock_table()
/drivers/gpu/drm/amd/pm/swsmu/inc/
A Damdgpu_smu.h922 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
/drivers/gpu/drm/amd/include/
A Dkgd_pp_interface.h511 struct dpm_clocks *clock_table);

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