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Searched refs:clr_bits (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/xe/
A Dxe_reg_sr.c57 if (e1->clr_bits & e2->clr_bits || e1->set_bits & e2->set_bits || in compatible_entries()
58 e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits) in compatible_entries()
88 pentry->clr_bits |= e->clr_bits; in xe_reg_sr_add()
111 idx, e->clr_bits, e->set_bits, in xe_reg_sr_add()
144 val = entry->clr_bits << 16; in apply_one_mmio()
145 else if (entry->clr_bits + 1) in apply_one_mmio()
148 xe_mmio_read32(&gt->mmio, reg)) & (~entry->clr_bits); in apply_one_mmio()
213 reg, entry->clr_bits, entry->set_bits, in xe_reg_sr_dump()
A Dxe_rtp.h244 .clr_bits = ~0u, .set_bits = (val_), \
262 .clr_bits = val_, .set_bits = val_, \
280 .clr_bits = val_, .set_bits = 0, \
297 .clr_bits = mask_bits_, .set_bits = val_, \
302 .clr_bits = (mask_bits_), .set_bits = (val_), \
318 .clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID, \
A Dxe_gt.c201 if (entry->reg.masked || entry->clr_bits == ~0) in emit_wa_job()
241 val = entry->clr_bits << 16; in emit_wa_job()
242 else if (entry->clr_bits == ~0) in emit_wa_job()
259 if (entry->reg.masked || entry->clr_bits == ~0) in emit_wa_job()
269 *cs++ = entry->clr_bits; in emit_wa_job()
288 entry->reg.addr, entry->clr_bits, entry->set_bits); in emit_wa_job()
A Dxe_reg_sr_types.h16 u32 clr_bits; member
A Dxe_rtp_types.h29 u32 clr_bits; member
A Dxe_rtp.c177 .clr_bits = action->clr_bits, in rtp_add_sr_entry()
A Dxe_reg_whitelist.c109 .clr_bits = ~0u, in whitelist_apply_to_hwe()
/drivers/media/platform/ti/omap3isp/
A Disp.h313 u32 reg, u32 clr_bits) in isp_reg_clr() argument
317 isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg); in isp_reg_clr()
348 u32 reg, u32 clr_bits, u32 set_bits) in isp_reg_clr_set() argument
352 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); in isp_reg_clr_set()
/drivers/gpu/drm/sprd/
A Dsprd_dpu.h83 dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits) in dpu_reg_clr() argument
87 writel(bits & ~clr_bits, ctx->base + offset); in dpu_reg_clr()
/drivers/tty/serial/
A Drp2.c233 u32 clr_bits, u32 set_bits) in rp2_rmw() argument
236 tmp &= ~clr_bits; in rp2_rmw()
/drivers/media/platform/qcom/camss/
A Dcamss-vfe-4-1.c221 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) in vfe_reg_clr() argument
225 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
A Dcamss-vfe-4-7.c265 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) in vfe_reg_clr() argument
269 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
A Dcamss-vfe-4-8.c248 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) in vfe_reg_clr() argument
252 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
/drivers/gpu/drm/xe/tests/
A Dxe_rtp_test.c336 KUNIT_EXPECT_EQ(test, sr_entry->clr_bits, param->expected_clr_bits); in xe_rtp_process_to_sr_tests()
/drivers/gpu/drm/i915/display/
A Dintel_ddi.c3060 u32 clr_bits, wait_bits; in mtl_ddi_disable_d2d() local
3067 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; in mtl_ddi_disable_d2d()
3071 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; in mtl_ddi_disable_d2d()
3075 intel_de_rmw(display, reg, clr_bits, 0); in mtl_ddi_disable_d2d()

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