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Searched refs:cmd_header (Results 1 – 25 of 32) sorted by relevance

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/drivers/net/wireless/marvell/libertas/
A Dhost.h367 struct cmd_header { struct
398 struct cmd_header hdr;
409 struct cmd_header hdr;
444 struct cmd_header hdr;
462 struct cmd_header hdr;
470 struct cmd_header hdr;
478 struct cmd_header hdr;
496 struct cmd_header hdr;
502 struct cmd_header hdr;
509 struct cmd_header hdr;
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A Dcmd.h21 struct cmd_header *);
24 struct cmd_header *cmdbuf;
44 struct cmd_header *in_cmd, int in_cmd_size);
47 struct cmd_header *in_cmd, int in_cmd_size,
48 int (*callback)(struct lbs_private *, unsigned long, struct cmd_header *),
52 uint16_t command, struct cmd_header *in_cmd, int in_cmd_size,
53 int (*callback)(struct lbs_private *, unsigned long, struct cmd_header *),
57 struct cmd_header *resp);
A Dcmd.c32 struct cmd_header *resp) in lbs_cmd_copyback()
34 struct cmd_header *buf = (void *)extra; in lbs_cmd_copyback()
55 struct cmd_header *resp) in lbs_cmd_async_callback()
164 struct cmd_header *resp) in lbs_ret_host_sleep_cfg()
351 struct cmd_header *cmd) in lbs_ret_host_sleep_activate()
361 struct cmd_header cmd; in lbs_set_host_sleep()
870 struct cmd_header *cmd; in lbs_submit_command()
1171 struct cmd_header *cmd; in lbs_execute_next_command()
1375 uint16_t command, struct cmd_header *in_cmd, int in_cmd_size, in __lbs_cmd_async()
1428 struct cmd_header *in_cmd, int in_cmd_size) in lbs_cmd_async()
[all …]
A Dcmdresp.c68 struct cmd_header *resp; in lbs_process_command_response()
225 struct cmd_header cmd; in lbs_process_event()
A Dif_sdio.c800 struct cmd_header cmd; in if_sdio_finish_power_on()
979 struct cmd_header cmd; in if_sdio_enter_deep_sleep()
1268 struct cmd_header cmd; in if_sdio_remove()
A Dif_usb.c388 struct cmd_header *cmd = cardp->ep_out_buf + 4; in if_usb_reset_device()
397 usb_tx_block(cardp, cardp->ep_out_buf, 4 + sizeof(struct cmd_header)); in if_usb_reset_device()
/drivers/net/wireless/marvell/libertas_tf/
A Dlibertas_tf.h318 struct cmd_header { struct
344 struct cmd_header hdr;
379 struct cmd_header hdr;
385 struct cmd_header hdr;
392 struct cmd_header hdr;
400 struct cmd_header hdr;
406 struct cmd_header hdr;
413 struct cmd_header hdr;
421 struct cmd_header hdr;
431 struct cmd_header hdr;
[all …]
A Dcmd.c43 struct cmd_header *resp) in lbtf_cmd_copyback()
45 struct cmd_header *buf = (void *)extra; in lbtf_cmd_copyback()
236 struct cmd_header *cmd; in lbtf_submit_command()
563 struct cmd_header *cmd; in lbtf_execute_next_command()
604 uint16_t command, struct cmd_header *in_cmd, int in_cmd_size, in __lbtf_cmd_async()
606 struct cmd_header *), in __lbtf_cmd_async() argument
654 struct cmd_header *in_cmd, int in_cmd_size) in lbtf_cmd_async()
662 struct cmd_header *in_cmd, int in_cmd_size, in __lbtf_cmd()
664 unsigned long, struct cmd_header *), in __lbtf_cmd() argument
715 struct cmd_header *resp; in lbtf_process_rx_command()
/drivers/gpu/drm/amd/amdgpu/
A Dmmsch_v3_0.h67 struct mmsch_v3_0_cmd_direct_reg_header cmd_header; member
72 struct mmsch_v3_0_cmd_direct_reg_header cmd_header; member
78 struct mmsch_v3_0_cmd_direct_reg_header cmd_header; member
84 struct mmsch_v3_0_cmd_direct_reg_header cmd_header; member
88 struct mmsch_v3_0_cmd_indirect_reg_header cmd_header; member
95 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
106 direct_wt.cmd_header.reg_offset = reg; \
116 direct_poll.cmd_header.reg_offset = reg; \
A Dmmsch_v4_0.h79 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; member
84 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; member
90 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; member
96 struct mmsch_v4_0_cmd_direct_reg_header cmd_header; member
100 struct mmsch_v4_0_cmd_indirect_reg_header cmd_header; member
107 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
118 direct_wt.cmd_header.reg_offset = reg; \
128 direct_poll.cmd_header.reg_offset = reg; \
A Dmmsch_v5_0.h78 struct mmsch_v5_0_cmd_direct_reg_header cmd_header; member
83 struct mmsch_v5_0_cmd_direct_reg_header cmd_header; member
89 struct mmsch_v5_0_cmd_direct_reg_header cmd_header; member
95 struct mmsch_v5_0_cmd_direct_reg_header cmd_header; member
99 struct mmsch_v5_0_cmd_indirect_reg_header cmd_header; member
106 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
117 direct_wt.cmd_header.reg_offset = reg; \
127 direct_poll.cmd_header.reg_offset = reg; \
A Dmmsch_v1_0.h72 struct mmsch_v1_0_cmd_direct_reg_header cmd_header; member
77 struct mmsch_v1_0_cmd_direct_reg_header cmd_header; member
83 struct mmsch_v1_0_cmd_direct_reg_header cmd_header; member
89 struct mmsch_v1_0_cmd_direct_reg_header cmd_header; member
93 struct mmsch_v1_0_cmd_indirect_reg_header cmd_header; member
102 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
112 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
124 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
A Dmmsch_v2_0.h256 struct mmsch_v2_0_cmd_direct_reg_header cmd_header; member
261 struct mmsch_v2_0_cmd_direct_reg_header cmd_header; member
267 struct mmsch_v2_0_cmd_direct_reg_header cmd_header; member
273 struct mmsch_v2_0_cmd_direct_reg_header cmd_header; member
277 struct mmsch_v2_0_cmd_indirect_reg_header cmd_header; member
286 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_wt()
296 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_rd_mod_wt()
308 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_poll()
A Dvce_v4_0.c217 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; in vce_v4_0_sriov_start()
218 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; in vce_v4_0_sriov_start()
219 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; in vce_v4_0_sriov_start()
220 end.cmd_header.command_type = MMSCH_COMMAND__END; in vce_v4_0_sriov_start()
A Djpeg_v4_0.c451 direct_wt.cmd_header.command_type = in jpeg_v4_0_start_sriov()
453 end.cmd_header.command_type = in jpeg_v4_0_start_sriov()
A Duvd_v7_0.c799 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; in uvd_v7_0_sriov_start()
800 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; in uvd_v7_0_sriov_start()
801 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; in uvd_v7_0_sriov_start()
802 end.cmd_header.command_type = MMSCH_COMMAND__END; in uvd_v7_0_sriov_start()
A Dvcn_v5_0_1.c738 direct_wt.cmd_header.command_type = in vcn_v5_0_1_start_sriov()
740 direct_rd_mod_wt.cmd_header.command_type = in vcn_v5_0_1_start_sriov()
742 end.cmd_header.command_type = MMSCH_COMMAND__END; in vcn_v5_0_1_start_sriov()
A Djpeg_v5_0_1.c460 direct_wt.cmd_header.command_type = in jpeg_v5_0_1_start_sriov()
462 end.cmd_header.command_type = in jpeg_v5_0_1_start_sriov()
A Dvcn_v4_0_3.c1016 direct_wt.cmd_header.command_type = in vcn_v4_0_3_start_sriov()
1018 direct_rd_mod_wt.cmd_header.command_type = in vcn_v4_0_3_start_sriov()
1020 end.cmd_header.command_type = MMSCH_COMMAND__END; in vcn_v4_0_3_start_sriov()
/drivers/gpu/drm/i915/
A Di915_cmd_parser.c738 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; in gen7_render_get_cmd_length_mask()
755 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) in gen7_bsd_get_cmd_length_mask() argument
757 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; in gen7_bsd_get_cmd_length_mask()
780 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; in gen7_blt_get_cmd_length_mask()
793 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; in gen9_blt_get_cmd_length_mask()
1078 u32 cmd_header) in find_cmd_in_table() argument
1083 cmd_header_key(cmd_header)) { in find_cmd_in_table()
1102 u32 cmd_header, in find_cmd() argument
1111 desc = find_cmd_in_table(engine, cmd_header); in find_cmd()
1115 mask = engine->get_cmd_length_mask(cmd_header); in find_cmd()
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/drivers/gpu/drm/imagination/
A Dpvr_cccb.c152 struct rogue_fwif_ccb_cmd_header cmd_header = { in pvr_cccb_write_command_with_header() local
192 memcpy(&pvr_cccb->cccb[pvr_cccb->write_offset], &cmd_header, sizeof(cmd_header)); in pvr_cccb_write_command_with_header()
193 memcpy(&pvr_cccb->cccb[pvr_cccb->write_offset + sizeof(cmd_header)], cmd_data, cmd_size); in pvr_cccb_write_command_with_header()
/drivers/scsi/qedi/
A Dqedi_fw_api.c589 struct iscsi_cmd_hdr *cmd_header, in init_initiator_rw_iscsi_task() argument
594 if (GET_FIELD(cmd_header->flags_attr, ISCSI_CMD_HDR_WRITE)) in init_initiator_rw_iscsi_task()
598 (struct iscsi_common_hdr *)cmd_header, in init_initiator_rw_iscsi_task()
601 else if (GET_FIELD(cmd_header->flags_attr, ISCSI_CMD_HDR_READ) || in init_initiator_rw_iscsi_task()
606 (struct iscsi_common_hdr *)cmd_header, in init_initiator_rw_iscsi_task()
/drivers/net/wireless/intel/iwlwifi/fw/
A Ddump.c99 u32 cmd_header; /* latest host cmd sent to UMAC */ member
167 IWL_ERR(fwrt, "0x%08X | last host cmd\n", table.cmd_header); in iwl_fwrt_dump_umac_error_log()
/drivers/gpu/drm/xe/
A Dxe_lrc.c1557 static int instr_dw(u32 cmd_header) in instr_dw() argument
1560 if ((cmd_header & (XE_INSTR_CMD_TYPE | GFXPIPE_PIPELINE)) == in instr_dw()
1565 if ((cmd_header & GFXPIPE_MATCH_MASK) == CMD_3DSTATE_SO_DECL_LIST) in instr_dw()
1566 return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2; in instr_dw()
1569 return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2; in instr_dw()
/drivers/gpu/drm/i915/gt/
A Dintel_engine_types.h619 u32 (*get_cmd_length_mask)(u32 cmd_header);

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