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Searched refs:cmd_reg (Results 1 – 17 of 17) sorted by relevance

/drivers/soc/qcom/
A Dramp_controller.c51 u8 cmd_reg; member
82 ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN); in rc_wait_for_update()
86 return regmap_read_poll_timeout(r, d->cmd_reg, val, !(val & RC_UPDATE_EN), in rc_wait_for_update()
108 ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce); in rc_set_cfg_update()
113 ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN); in rc_set_cfg_update()
118 ret = regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, val, in rc_set_cfg_update()
129 ret = regmap_write(r, d->cmd_reg + RC_REG_CFG_UPDATE, 0); in rc_set_cfg_update()
134 return regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, in rc_set_cfg_update()
282 .cmd_reg = 0x0,
/drivers/crypto/ccp/
A Dplatform-access.c63 u32 cmd_reg; in psp_send_platform_access_msg() local
106 cmd_reg = FIELD_PREP(PSP_CMDRESP_CMD, msg); in psp_send_platform_access_msg()
107 iowrite32(cmd_reg, cmd); in psp_send_platform_access_msg()
128 cmd_reg = ioread32(cmd); in psp_send_platform_access_msg()
129 if (FIELD_GET(PSP_CMDRESP_STS, cmd_reg)) in psp_send_platform_access_msg()
130 req->header.status = FIELD_GET(PSP_CMDRESP_STS, cmd_reg); in psp_send_platform_access_msg()
/drivers/mtd/nand/raw/
A Dloongson1-nand-controller.c59 unsigned int cmd_reg; member
109 op->cmd_reg = LS1X_NAND_CMD_STATUS; in ls1x_nand_op_cmd_mapping()
112 op->cmd_reg = LS1X_NAND_CMD_RESET; in ls1x_nand_op_cmd_mapping()
116 op->cmd_reg = LS1X_NAND_CMD_READID; in ls1x_nand_op_cmd_mapping()
127 op->cmd_reg = LS1X_NAND_CMD_ERASE; in ls1x_nand_op_cmd_mapping()
135 op->cmd_reg = LS1X_NAND_CMD_WRITE; in ls1x_nand_op_cmd_mapping()
143 op->cmd_reg = LS1X_NAND_CMD_READ; in ls1x_nand_op_cmd_mapping()
151 op->cmd_reg = LS1X_NAND_CMD_READ; in ls1x_nand_op_cmd_mapping()
291 op->cmd_reg |= LS1X_NAND_CMD_OP_MAIN; in ls1x_nand_trigger_op()
295 op->cmd_reg |= LS1X_NAND_CMD_OP_SPARE; in ls1x_nand_trigger_op()
[all …]
A Darasan-nand-controller.c140 u32 cmd_reg; member
277 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG); in anfc_trigger_op()
413 .cmd_reg = in anfc_read_page_hw_ecc()
531 .cmd_reg = in anfc_write_page_hw_ecc()
608 nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz); in anfc_parse_instructions()
620 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode); in anfc_parse_instructions()
622 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode); in anfc_parse_instructions()
631 nfc_op->cmd_reg |= CMD_NADDRS(naddrs); in anfc_parse_instructions()
A Dqcom_nandc.c52 __le32 cmd_reg; member
1620 q_op->cmd_reg = cpu_to_le32(ret); in qcom_parse_instructions()
1717 nandc->regs->cmd = q_op.cmd_reg; in qcom_read_status_exec()
1774 nandc->regs->cmd = q_op.cmd_reg; in qcom_read_id_type_exec()
1816 } else if (q_op.cmd_reg == cpu_to_le32(OP_BLOCK_ERASE)) { in qcom_misc_cmd_type_exec()
1817 q_op.cmd_reg |= cpu_to_le32(PAGE_ACC | LAST_PAGE); in qcom_misc_cmd_type_exec()
1823 } else if (q_op.cmd_reg != cpu_to_le32(OP_RESET_DEVICE)) { in qcom_misc_cmd_type_exec()
1834 nandc->regs->cmd = q_op.cmd_reg; in qcom_misc_cmd_type_exec()
1838 if (q_op.cmd_reg == cpu_to_le32(OP_BLOCK_ERASE)) in qcom_misc_cmd_type_exec()
1877 q_op.cmd_reg |= cpu_to_le32(PAGE_ACC | LAST_PAGE); in qcom_param_page_type_exec()
[all …]
/drivers/mmc/host/
A Ddavinci_mmc.c260 u32 cmd_reg = 0; in mmc_davinci_start_command() local
291 cmd_reg |= MMCCMD_BSYEXP; in mmc_davinci_start_command()
297 cmd_reg |= MMCCMD_RSPFMT_R2; in mmc_davinci_start_command()
300 cmd_reg |= MMCCMD_RSPFMT_R3; in mmc_davinci_start_command()
303 cmd_reg |= MMCCMD_RSPFMT_NONE; in mmc_davinci_start_command()
310 cmd_reg |= cmd->opcode; in mmc_davinci_start_command()
314 cmd_reg |= MMCCMD_DMATRIG; in mmc_davinci_start_command()
318 cmd_reg |= MMCCMD_DMATRIG; in mmc_davinci_start_command()
322 cmd_reg |= MMCCMD_WDATX; in mmc_davinci_start_command()
326 cmd_reg |= MMCCMD_DTRW; in mmc_davinci_start_command()
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A Dsdhci-uhs2.c637 int cmd_reg; in __sdhci_uhs2_send_command() local
665 cmd_reg = FIELD_PREP(SDHCI_UHS2_CMD_PACK_LEN_MASK, cmd->uhs2_cmd->packet_len); in __sdhci_uhs2_send_command()
667 cmd_reg |= SDHCI_UHS2_CMD_DATA; in __sdhci_uhs2_send_command()
669 cmd_reg |= SDHCI_UHS2_CMD_CMD12; in __sdhci_uhs2_send_command()
674 cmd_reg |= SDHCI_UHS2_CMD_TRNS_ABORT; in __sdhci_uhs2_send_command()
679 cmd_reg |= SDHCI_UHS2_CMD_DORMANT; in __sdhci_uhs2_send_command()
681 DBG("0x%x is set to UHS2 CMD register.\n", cmd_reg); in __sdhci_uhs2_send_command()
683 sdhci_writew(host, cmd_reg, SDHCI_UHS2_CMD); in __sdhci_uhs2_send_command()
/drivers/parisc/
A Dled.c395 int __init register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg) in register_led_driver() argument
405 LCD_CMD_REG = (cmd_reg == LED_CMD_REG_NONE) ? 0 : cmd_reg; in register_led_driver()
/drivers/cxl/
A Dpci.c205 u64 cmd_reg, status_reg; in __cxl_pci_mbox_send_cmd() local
248 cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, in __cxl_pci_mbox_send_cmd()
254 cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, in __cxl_pci_mbox_send_cmd()
260 writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); in __cxl_pci_mbox_send_cmd()
353 cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); in __cxl_pci_mbox_send_cmd()
354 out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); in __cxl_pci_mbox_send_cmd()
/drivers/scsi/aic94xx/
A Daic94xx_init.c140 u16 cmd_reg; in asd_map_ha() local
142 err = pci_read_config_word(asd_ha->pcidev, PCI_COMMAND, &cmd_reg); in asd_map_ha()
150 if (cmd_reg & PCI_COMMAND_MEMORY) { in asd_map_ha()
153 } else if (cmd_reg & PCI_COMMAND_IO) { in asd_map_ha()
/drivers/gpu/drm/i915/gvt/
A Dcmd_parser.c1036 #define cmd_reg(s, i) \ macro
1056 cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR)) in cmd_handler_lri()
1063 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri"); in cmd_handler_lri()
1082 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src"); in cmd_handler_lrr()
1085 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst"); in cmd_handler_lrr()
1108 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm"); in cmd_handler_lrm()
1132 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm"); in cmd_handler_srm()
1195 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl"); in cmd_handler_pipe_control()
/drivers/hid/intel-thc-hid/intel-quicki2c/
A Dquicki2c-protocol.c33 memcpy(write_buf, &qcdev->dev_desc.cmd_reg, HIDI2C_REG_LEN); in quicki2c_init_write_buf()
/drivers/atm/
A Diphase.h649 ffreg_t cmd_reg; /* Command register */ member
729 rreg_t cmd_reg; /* Command register */ member
/drivers/dma/qcom/
A Dgpi.c676 void __iomem *cmd_reg; in gpi_send_cmd() local
691 cmd_reg = IS_CHAN_CMD(gpi_cmd) ? gchan->ch_cmd_reg : gpii->ev_cmd_reg; in gpi_send_cmd()
694 gpi_write_reg(gpii, cmd_reg, cmd); in gpi_send_cmd()
/drivers/usb/host/
A Dxhci-ring.c1987 u32 portsc, cmd_reg; in handle_port_status() local
2047 cmd_reg = readl(&xhci->op_regs->command); in handle_port_status()
2048 if (!(cmd_reg & CMD_RUN)) { in handle_port_status()
/drivers/scsi/
A Dadvansys.c8665 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) in AscWriteEEPCmdReg() argument
8671 AscSetChipEEPCmd(iop_base, cmd_reg); in AscWriteEEPCmdReg()
8674 if (read_back == cmd_reg) in AscWriteEEPCmdReg()
8688 uchar cmd_reg; in AscReadEEPWord() local
8692 cmd_reg = addr | ASC_EEP_CMD_READ; in AscReadEEPWord()
8693 AscWriteEEPCmdReg(iop_base, cmd_reg); in AscReadEEPWord()
A Dipr.c8140 u16 cmd_reg; in ipr_reset_alert() local
8144 rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg); in ipr_reset_alert()
8146 if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) { in ipr_reset_alert()

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