| /drivers/infiniband/hw/bnxt_re/ |
| A D | qplib_tlv.h | 51 return ((struct cmdq_base *)GET_TLV_DATA(req))->opcode; in __get_cmdq_base_opcode()
60 ((struct cmdq_base *)GET_TLV_DATA(req))->opcode = val; in __set_cmdq_base_opcode()
68 return ((struct cmdq_base *)GET_TLV_DATA(req))->cookie; in __get_cmdq_base_cookie()
77 ((struct cmdq_base *)GET_TLV_DATA(req))->cookie = val; in __set_cmdq_base_cookie()
85 return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr; in __get_cmdq_base_resp_addr()
94 ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr = val; in __set_cmdq_base_resp_addr()
102 return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_size; in __get_cmdq_base_resp_size()
111 ((struct cmdq_base *)GET_TLV_DATA(req))->resp_size = val; in __set_cmdq_base_resp_size()
128 ((struct cmdq_base *)GET_TLV_DATA(req))->cmd_size = val; in __set_cmdq_base_cmd_size()
136 return ((struct cmdq_base *)GET_TLV_DATA(req))->flags; in __get_cmdq_base_flags()
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| A D | qplib_rcfw.h | 63 static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req, in bnxt_qplib_rcfw_cmd_prep()
97 static inline u32 bnxt_qplib_get_cmd_slots(struct cmdq_base *req) in bnxt_qplib_get_cmd_slots()
113 static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req) in bnxt_qplib_set_cmd_slots()
242 struct cmdq_base *req;
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| A D | qplib_sp.c | 77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_version()
105 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_get_dev_attr()
212 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_set_func_resources()
281 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_del_sgid()
413 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_update_sgid()
452 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_ah()
497 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_ah()
523 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_free_mrw()
558 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_alloc_mrw()
596 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_dereg_mrw()
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| A D | qplib_rcfw.c | 458 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in __destroy_timedout_ah()
462 msg.req = (struct cmdq_base *)&req; in __destroy_timedout_ah()
816 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_deinit_rcfw()
839 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_init_rcfw()
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| A D | qplib_fp.c | 627 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_srq()
663 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_srq()
749 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_srq()
860 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_qp1()
1006 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_qp()
1347 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_modify_qp()
1476 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_query_qp()
1609 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_destroy_qp()
2242 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_create_cq()
2328 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_resize_cq()
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| A D | roce_hsi.h | 104 struct cmdq_base { struct
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| /drivers/gpu/drm/mediatek/ |
| A D | mtk_ethdr.c | 73 struct cmdq_client_reg cmdq_base; member
228 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, in mtk_ethdr_config()
231 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, in mtk_ethdr_config()
234 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, in mtk_ethdr_config()
237 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, in mtk_ethdr_config()
240 mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base, in mtk_ethdr_config()
247 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
249 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
257 &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON); in mtk_ethdr_config()
258 mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
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| /drivers/soc/mediatek/ |
| A D | mtk-mmsys.c | 160 struct cmdq_client_reg cmdq_base; member
169 if (mmsys->cmdq_base.size && cmdq_pkt) { in mtk_mmsys_update_bits()
170 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, in mtk_mmsys_update_bits()
171 mmsys->cmdq_base.offset + offset, val, in mtk_mmsys_update_bits()
423 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); in mtk_mmsys_probe()
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| /drivers/accel/ivpu/ |
| A D | ivpu_jsm_msg.c | 287 u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size) in ivpu_jsm_hws_create_cmdq() argument
298 req.payload.hws_create_cmdq.cmdq_base = cmdq_base; in ivpu_jsm_hws_create_cmdq()
327 u64 cmdq_base, u32 cmdq_size) in ivpu_jsm_hws_register_db() argument
336 req.payload.hws_register_db.cmdq_base = cmdq_base; in ivpu_jsm_hws_register_db()
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| A D | ivpu_jsm_msg.h | 27 u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size);
30 u64 cmdq_base, u32 cmdq_size);
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| A D | vpu_jsm_api.h | 989 u64 cmdq_base; member
1071 u64 cmdq_base; member
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