Searched refs:com_integloop_gain1_mode0 (Results 1 – 2 of 2) sorted by relevance
54 u32 com_integloop_gain1_mode0; member299 cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8); in pll_calculate()372 DBG("com_integloop_gain1_mode0 = 0x%x", cfg->com_integloop_gain1_mode0); in pll_calculate()482 cfg.com_integloop_gain1_mode0); in hdmi_8996_pll_set_clk_rate()
54 u32 com_integloop_gain1_mode0; member343 cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8); in pll_calculate()516 cfg.com_integloop_gain1_mode0); in hdmi_8998_pll_set_clk_rate()
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