Searched refs:component_reg_phys (Results 1 – 5 of 5) sorted by relevance
| /drivers/cxl/core/ |
| A D | port.c | 759 .resource = component_reg_phys, in cxl_setup_comp_regs()
772 resource_size_t component_reg_phys) in cxl_port_setup_regs() argument
777 component_reg_phys); in cxl_port_setup_regs()
781 resource_size_t component_reg_phys) in cxl_dport_setup_regs() argument
794 component_reg_phys); in cxl_dport_setup_regs()
834 resource_size_t component_reg_phys, in cxl_port_add() argument
922 resource_size_t component_reg_phys, in devm_cxl_add_port() argument
1143 component_reg_phys); in __devm_cxl_add_dport()
1168 &component_reg_phys); in __devm_cxl_add_dport()
1541 resource_size_t component_reg_phys; in add_port_attach_ep() local
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| A D | regs.c | 580 resource_size_t component_reg_phys; in __rcrb_to_component() local
623 component_reg_phys = bar0 & PCI_BASE_ADDRESS_MEM_MASK; in __rcrb_to_component()
625 component_reg_phys |= ((u64)bar1) << 32; in __rcrb_to_component()
627 if (!component_reg_phys) in __rcrb_to_component()
631 if (!IS_ALIGNED(component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE)) in __rcrb_to_component()
634 return component_reg_phys; in __rcrb_to_component()
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| /drivers/cxl/ |
| A D | acpi.c | 696 resource_size_t component_reg_phys; in add_host_bridge_uport() local
725 component_reg_phys = ctx.base; in add_host_bridge_uport()
726 if (component_reg_phys != CXL_RESOURCE_NONE) in add_host_bridge_uport()
728 ctx.uid, &component_reg_phys); in add_host_bridge_uport()
734 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport); in add_host_bridge_uport()
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| A D | pci.c | 481 resource_size_t component_reg_phys; in cxl_rcrb_get_comp_regs() local
493 component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); in cxl_rcrb_get_comp_regs()
494 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_rcrb_get_comp_regs()
497 map->resource = component_reg_phys; in cxl_rcrb_get_comp_regs()
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| A D | cxl.h | 738 resource_size_t component_reg_phys,
760 resource_size_t component_reg_phys);
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