Searched refs:con0 (Results 1 – 5 of 5) sorted by relevance
| /drivers/pwm/ |
| A D | pwm-mtk-disp.c | 32 unsigned int con0; member
144 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_apply()
149 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_apply()
178 u32 clk_div, pwm_en, con0, con1; in mtk_disp_pwm_get_state() local
205 con0 = readl(mdp->base + mdp->data->con0); in mtk_disp_pwm_get_state()
209 clk_div = FIELD_GET(PWM_CLKDIV_MASK, con0); in mtk_disp_pwm_get_state()
269 .con0 = 0xa8,
279 .con0 = 0x10,
289 .con0 = 0x18,
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| /drivers/clk/samsung/ |
| A D | clk-pll.c | 681 u32 con0, con1; in samsung_pll45xx_set_rate() local
691 con0 = readl_relaxed(pll->con_reg); in samsung_pll45xx_set_rate()
698 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
730 writel_relaxed(con0, pll->con_reg); in samsung_pll45xx_set_rate()
818 u32 con0, con1, lock; in samsung_pll46xx_set_rate() local
828 con0 = readl_relaxed(pll->con_reg); in samsung_pll46xx_set_rate()
835 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
874 writel_relaxed(con0, pll->con_reg); in samsung_pll46xx_set_rate()
1151 u32 con0, con1; in samsung_pll2650x_set_rate() local
1161 con0 = readl_relaxed(pll->con_reg); in samsung_pll2650x_set_rate()
[all …]
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| /drivers/video/fbdev/ |
| A D | pxa168fb.h | 357 #define CFG_COS0(con0) (con0) argument
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| /drivers/net/ethernet/stmicro/stmmac/ |
| A D | dwmac-rk.c | 989 u32 con0, con1; in rk3568_set_to_rgmii() local
991 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : in rk3568_set_to_rgmii()
996 regmap_write(bsp_priv->grf, con0, in rk3568_set_to_rgmii()
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| /drivers/video/fbdev/mmp/hw/ |
| A D | mmp_ctrl.h | 585 #define CFG_COS0(con0) (con0) argument
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