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Searched refs:config_base (Results 1 – 25 of 36) sorted by relevance

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/drivers/perf/
A Darm_v7_pmu.c1001 unsigned long config_base = 0; in armv7pmu_set_event_filter() local
1008 config_base |= ARMV7_EXCLUDE_USER; in armv7pmu_set_event_filter()
1010 config_base |= ARMV7_EXCLUDE_PL1; in armv7pmu_set_event_filter()
1012 config_base |= ARMV7_INCLUDE_HYP; in armv7pmu_set_event_filter()
1018 event->config_base = config_base; in armv7pmu_set_event_filter()
1438 if (hwc->config_base & KRAIT_EVENT_MASK) in krait_pmu_disable_event()
1439 krait_clearpmu(hwc->config_base); in krait_pmu_disable_event()
1455 if (hwc->config_base & KRAIT_EVENT_MASK) in krait_pmu_enable_event()
1496 if (hwc->config_base & VENUM_EVENT) in krait_event_to_bit()
1749 scorpion_clearpmu(hwc->config_base); in scorpion_pmu_disable_event()
[all …]
A Dapple_m1_cpu_pmu.c411 bool guest = config_base & M1_PMU_CFG_COUNT_GUEST; in m1_pmu_configure_counter()
412 bool host = config_base & M1_PMU_CFG_COUNT_HOST; in m1_pmu_configure_counter()
413 bool user = config_base & M1_PMU_CFG_COUNT_USER; in m1_pmu_configure_counter()
414 u8 evt = config_base & M1_PMU_CFG_EVENT; in m1_pmu_configure_counter()
427 evt = event->hw.config_base & M1_PMU_CFG_EVENT; in m1_pmu_enable_event()
606 unsigned long config_base = 0; in m1_pmu_set_event_filter() local
613 config_base |= M1_PMU_CFG_COUNT_KERNEL; in m1_pmu_set_event_filter()
615 config_base |= M1_PMU_CFG_COUNT_USER; in m1_pmu_set_event_filter()
617 config_base |= M1_PMU_CFG_COUNT_HOST; in m1_pmu_set_event_filter()
619 config_base |= M1_PMU_CFG_COUNT_GUEST; in m1_pmu_set_event_filter()
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A Darm_pmuv3.c674 write_pmccfiltr(hwc->config_base); in armv8pmu_write_event_type()
676 write_pmicfiltr(hwc->config_base); in armv8pmu_write_event_type()
678 armv8pmu_write_evtype(idx, hwc->config_base); in armv8pmu_write_event_type()
1058 unsigned long config_base = 0; in armv8pmu_set_event_filter() local
1084 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
1086 config_base |= ARMV8_PMU_EXCLUDE_EL1; in armv8pmu_set_event_filter()
1088 config_base |= ARMV8_PMU_EXCLUDE_EL0; in armv8pmu_set_event_filter()
1091 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
1098 config_base |= ARMV8_PMU_EXCLUDE_EL1; in armv8pmu_set_event_filter()
1101 config_base |= ARMV8_PMU_EXCLUDE_EL0; in armv8pmu_set_event_filter()
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A Darm_xscale_pmu.c216 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
221 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
270 if (XSCALE_PERFCTR_CCNT == hwc->config_base) { in xscale1pmu_get_event_idx()
551 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; in xscale2pmu_enable_event()
556 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; in xscale2pmu_enable_event()
561 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; in xscale2pmu_enable_event()
566 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; in xscale2pmu_enable_event()
A Dthunderx2_pmu.c332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
378 reg_writel(val, hwc->config_base); in uncore_start_event_l3c()
385 reg_writel(0, event->hw.config_base); in uncore_stop_event_l3c()
405 val = reg_readl(hwc->config_base); in uncore_start_event_dmc()
408 reg_writel(val, hwc->config_base); in uncore_start_event_dmc()
425 val = reg_readl(hwc->config_base); in uncore_stop_event_dmc()
427 reg_writel(val, hwc->config_base); in uncore_stop_event_dmc()
445 GET_EVENTID(event, emask)), hwc->config_base); in uncore_start_event_ccpi2()
A Dqcom_l2_pmu.c347 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_get_event_idx()
364 group = L2_EVT_GROUP(hwc->config_base); in l2_cache_get_event_idx()
381 if (hwc->config_base != L2CYCLE_CTR_RAW_CODE) in l2_cache_clear_event_idx()
382 clear_bit(L2_EVT_GROUP(hwc->config_base), cluster->used_groups); in l2_cache_clear_event_idx()
530 hwc->config_base = event->attr.config; in l2_cache_event_init()
555 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_event_start()
558 config = hwc->config_base; in l2_cache_event_start()
A Darm_v6_pmu.c216 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | in armv6pmu_enable_event()
220 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | in armv6pmu_enable_event()
318 if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) { in armv6pmu_get_event_idx()
A Darm-ccn.c673 hw->config_base = bit; in arm_ccn_pmu_event_alloc()
694 clear_bit(hw->config_base, source->xp.dt_cmp_mask); in arm_ccn_pmu_event_release()
696 clear_bit(hw->config_base, source->pmu_events_mask); in arm_ccn_pmu_event_release()
940 unsigned long wp = hw->config_base; in arm_ccn_pmu_xp_watchpoint_config()
990 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
998 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_xp_event_config()
999 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1014 hw->config_base); in arm_ccn_pmu_node_event_config()
1034 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_node_event_config()
1036 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_node_event_config()
A Darm-cci.c789 unsigned long cci_event = event->hw.config_base; in pmu_get_event_idx()
960 pmu_set_event(cci_pmu, i, event->hw.config_base); in cci5xx_pmu_write_counters()
1145 pmu_set_event(cci_pmu, idx, hwc->config_base); in cci_pmu_start()
1286 hwc->config_base = 0; in __hw_perf_event_init()
1293 hwc->config_base |= (unsigned long)mapping; in __hw_perf_event_init()
A Darm_dsu_pmu.c327 __dsu_pmu_set_event(idx, event->hw.config_base); in dsu_pmu_set_event()
566 event->hw.config_base = event->attr.config; in dsu_pmu_event_init()
A Darm_pmu.c475 hwc->config_base = 0; in __hw_perf_event_init()
491 hwc->config_base |= (unsigned long)mapping; in __hw_perf_event_init()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_pmu.c219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE; in amdgpu_perf_event_init()
243 switch (hwc->config_base) { in amdgpu_perf_start()
281 switch (hwc->config_base) { in amdgpu_perf_read()
311 switch (hwc->config_base) { in amdgpu_perf_stop()
346 hwc->config_base = AMDGPU_PMU_EVENT_CONFIG_TYPE_DF; in amdgpu_perf_add()
349 hwc->config_base = (hwc->config >> in amdgpu_perf_add()
357 switch (hwc->config_base) { in amdgpu_perf_add()
395 switch (hwc->config_base) { in amdgpu_perf_del()
/drivers/pci/controller/dwc/
A Dpcie-tegra194-acpi.c17 void __iomem *config_base; member
31 pcie_ecam->config_base = cfg->win; in tegra194_acpi_init()
99 return pcie_ecam->config_base + where; in tegra194_map_bus()
/drivers/pci/controller/
A Dpci-v3-semi.c239 void __iomem *config_base; member
378 return v3->config_base + address + offset; in v3_map_bus()
757 v3->config_base = devm_ioremap_resource(dev, regs); in v3_pci_probe()
758 if (IS_ERR(v3->config_base)) in v3_pci_probe()
759 return PTR_ERR(v3->config_base); in v3_pci_probe()
/drivers/pci/controller/plda/
A Dpcie-plda-host.c28 return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in plda_pcie_map_bus()
595 port->config_base = devm_ioremap_resource(dev, cfg_res); in plda_pcie_host_init()
596 if (IS_ERR(port->config_base)) in plda_pcie_host_init()
597 return dev_err_probe(dev, PTR_ERR(port->config_base), in plda_pcie_host_init()
A Dpcie-plda.h184 void __iomem *config_base; member
/drivers/media/dvb-core/
A Ddvb_ca_en50221.c94 u32 config_base; member
523 sl->config_base = 0; in dvb_ca_en50221_parse_attributes()
525 sl->config_base |= (tuple[2 + i] << (8 * i)); in dvb_ca_en50221_parse_attributes()
589 manfid, devid, sl->config_base, sl->config_option); in dvb_ca_en50221_parse_attributes()
609 ca->pub->write_attribute_mem(ca->pub, slot, sl->config_base, in dvb_ca_en50221_set_configoption()
614 sl->config_base); in dvb_ca_en50221_set_configoption()
/drivers/net/ethernet/fujitsu/
A Dfmvj18x_cs.c359 link->config_base = 0x800; in fmvj18x_config()
366 link->config_base = 0x800; in fmvj18x_config()
372 link->config_base = 0x800; in fmvj18x_config()
380 if (link->config_base == 0x0fe0) in fmvj18x_config()
/drivers/tty/serial/8250/
A D8250_pci.c1658 u8 config_base; in pci_fintek_setup() local
1664 config_base = 0x40 + 0x08 * idx; in pci_fintek_setup()
1667 pci_read_config_word(pdev, config_base + 4, &iobase); in pci_fintek_setup()
1692 u8 config_base; in pci_fintek_init() local
1722 config_base = 0x40 + 0x08 * i; in pci_fintek_init()
1728 pci_write_config_byte(dev, config_base + 0x00, 0x01); in pci_fintek_init()
1734 pci_write_config_byte(dev, config_base + 0x04, in pci_fintek_init()
1738 pci_write_config_byte(dev, config_base + 0x05, in pci_fintek_init()
1791 int config_base; in pci_fintek_f815xxa_init() local
1813 config_base = 0x2A0 + 0x08 * i; in pci_fintek_f815xxa_init()
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/drivers/fpga/
A Ddfl-fme-perf.c792 ops->event_destroy(priv, event->hw.idx, event->hw.config_base); in fme_perf_event_destroy()
828 hwc->config_base = portid; in fme_perf_event_init()
849 now = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); in fme_perf_event_update()
863 count = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); in fme_perf_event_start()
/drivers/perf/hisilicon/
A Dhisi_uncore_pmu.h46 #define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
/drivers/pcmcia/
A Dpcmcia_resource.c177 addr = (p_dev->config_base + where) >> 1; in pcmcia_access_config()
535 p_dev->vpp, flags, p_dev->config_base, p_dev->config_regs, in pcmcia_enable_device()
539 base = p_dev->config_base; in pcmcia_enable_device()
/drivers/mfd/
A Dqcom-pm8008.c154 .config_base = pm8008_config_regs,
A Dwcd934x.c70 .config_base = wcd934x_config_regs,
/drivers/net/can/sja1000/
A Dems_pcmcia.c283 csval = pcmcia_map_mem_page(dev, dev->resource[2], dev->config_base); in ems_pcmcia_probe()

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