Home
last modified time | relevance | path

Searched refs:controller_id (Results 1 – 25 of 89) sorted by relevance

1234

/drivers/gpu/drm/amd/display/dc/hwss/dce120/
A Ddce120_hwseq.c79 #define CNTL_ID(controller_id)\
80 controller_id
84 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
153 uint8_t controller_id, in dce120_enable_display_power_gating() argument
170 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { in dce120_enable_display_power_gating()
173 dcb, controller_id + 1, cntl); in dce120_enable_display_power_gating()
179 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id), in dce120_enable_display_power_gating()
184 dce120_init_pte(ctx, controller_id); in dce120_enable_display_power_gating()
/drivers/gpu/drm/amd/display/dc/bios/
A Dcommand_table.h76 enum controller_id controller_id,
80 enum controller_id controller_id,
90 enum controller_id crtc_id,
A Dcommand_table2.h76 enum controller_id controller_id,
80 enum controller_id controller_id,
90 enum controller_id crtc_id,
A Dcommand_table2.c485 uint8_t controller_id; in set_pixel_clock_v7() local
492 controller_id, &controller_id)) { in set_pixel_clock_v7()
512 clk.crtc_id = controller_id; in set_pixel_clock_v7()
532 bp_params->target_pixel_clock_100hz, (int)controller_id, in set_pixel_clock_v7()
614 bp_params->controller_id, &atom_controller_id)) in set_crtc_using_dtd_timing_v3()
706 enum controller_id controller_id,
723 enum controller_id controller_id, in enable_crtc_v1() argument
800 enum controller_id crtc_id,
805 enum controller_id crtc_id,
845 enum controller_id crtc_id, in enable_disp_power_gating_v2_1()
[all …]
A Dcommand_table.c1052 uint8_t controller_id; in set_pixel_clock_v5() local
1059 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v5()
1122 uint8_t controller_id; in set_pixel_clock_v6() local
1129 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v6()
1214 uint8_t controller_id; in set_pixel_clock_v7() local
1220 && bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) { in set_pixel_clock_v7()
1987 enum controller_id controller_id,
2006 enum controller_id controller_id, in enable_crtc_v1() argument
2039 enum controller_id controller_id,
2056 enum controller_id controller_id, in enable_crtc_mem_req_v1() argument
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_abm.c58 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst) in dce_abm_set_pipe() argument
75 MASTER_COMM_CMD_REG_BYTE1, controller_id); in dce_abm_set_pipe()
90 uint32_t controller_id, in dmcu_set_backlight_level() argument
103 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id); in dmcu_set_backlight_level()
113 if (controller_id == 0) in dmcu_set_backlight_level()
234 unsigned int controller_id, in dce_abm_set_backlight_level_pwm() argument
245 controller_id, in dce_abm_set_backlight_level_pwm()
A Ddce_clock_source.c863 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce110_program_pix_clk()
937 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce112_program_pix_clk()
972 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn31_program_pix_clk()
1016 bp_pc_params.controller_id = pix_clk_params->controller_id; in dcn31_program_pix_clk()
1074 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn401_program_pix_clk()
1118 bp_pc_params.controller_id = pix_clk_params->controller_id; in dcn401_program_pix_clk()
1180 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; in dce110_clock_source_power_down()
1288 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn20_program_pix_clk()
1334 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn3_program_pix_clk()
/drivers/gpu/drm/amd/display/include/
A Dbios_parser_types.h137 enum controller_id controller_id; member
170 enum controller_id controller_id; member
218 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ member
A Dgrph_object_id.h74 enum controller_id { enum
255 static inline enum controller_id dal_graphics_object_id_get_controller_id( in dal_graphics_object_id_get_controller_id()
259 return (enum controller_id) id.id; in dal_graphics_object_id_get_controller_id()
/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_8_0_sc8280xp.h297 .controller_id = MSM_DP_CONTROLLER_0,
305 .controller_id = MSM_DSI_CONTROLLER_0,
314 .controller_id = MSM_DSI_CONTROLLER_1,
323 .controller_id = MSM_DP_CONTROLLER_0,
331 .controller_id = MSM_DP_CONTROLLER_1,
339 .controller_id = MSM_DP_CONTROLLER_3,
347 .controller_id = MSM_DP_CONTROLLER_2,
355 .controller_id = MSM_DP_CONTROLLER_2,
363 .controller_id = MSM_DP_CONTROLLER_1,
A Ddpu_9_2_x1e80100.h313 .controller_id = MSM_DP_CONTROLLER_0,
321 .controller_id = MSM_DSI_CONTROLLER_0,
330 .controller_id = MSM_DSI_CONTROLLER_1,
339 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
347 .controller_id = MSM_DP_CONTROLLER_1,
355 .controller_id = MSM_DP_CONTROLLER_3,
363 .controller_id = MSM_DP_CONTROLLER_2,
371 .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
379 .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
A Ddpu_8_4_sa8775p.h325 .controller_id = MSM_DP_CONTROLLER_0,
333 .controller_id = MSM_DSI_CONTROLLER_0,
342 .controller_id = MSM_DSI_CONTROLLER_1,
351 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
359 .controller_id = MSM_DP_CONTROLLER_1,
367 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
375 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
383 .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
A Ddpu_5_1_sc8180x.h300 .controller_id = MSM_DP_CONTROLLER_0,
308 .controller_id = MSM_DSI_CONTROLLER_0,
317 .controller_id = MSM_DSI_CONTROLLER_1,
328 .controller_id = 999,
336 .controller_id = MSM_DP_CONTROLLER_1,
344 .controller_id = MSM_DP_CONTROLLER_2,
A Ddpu_5_2_sm7150.h207 .controller_id = MSM_DP_CONTROLLER_0,
215 .controller_id = MSM_DSI_CONTROLLER_0,
224 .controller_id = MSM_DSI_CONTROLLER_1,
233 .controller_id = MSM_DP_CONTROLLER_1,
A Ddpu_4_0_sdm845.h237 .controller_id = MSM_DP_CONTROLLER_0,
245 .controller_id = MSM_DSI_CONTROLLER_0,
253 .controller_id = MSM_DSI_CONTROLLER_1,
261 .controller_id = MSM_DP_CONTROLLER_1,
A Ddpu_5_0_sm8150.h294 .controller_id = MSM_DP_CONTROLLER_0,
302 .controller_id = MSM_DSI_CONTROLLER_0,
311 .controller_id = MSM_DSI_CONTROLLER_1,
320 .controller_id = MSM_DP_CONTROLLER_1,
A Ddpu_6_0_sm8250.h278 .controller_id = MSM_DP_CONTROLLER_0,
286 .controller_id = MSM_DSI_CONTROLLER_0,
295 .controller_id = MSM_DSI_CONTROLLER_1,
304 .controller_id = MSM_DP_CONTROLLER_1,
A Ddpu_7_0_sm8350.h304 .controller_id = MSM_DP_CONTROLLER_0,
312 .controller_id = MSM_DSI_CONTROLLER_0,
321 .controller_id = MSM_DSI_CONTROLLER_1,
330 .controller_id = MSM_DP_CONTROLLER_1,
A Ddpu_9_0_sm8550.h312 .controller_id = MSM_DP_CONTROLLER_0,
320 .controller_id = MSM_DSI_CONTROLLER_0,
329 .controller_id = MSM_DSI_CONTROLLER_1,
338 .controller_id = MSM_DP_CONTROLLER_1,
A Ddpu_9_1_sar2130p.h312 .controller_id = MSM_DP_CONTROLLER_0,
320 .controller_id = MSM_DSI_CONTROLLER_0,
329 .controller_id = MSM_DSI_CONTROLLER_1,
338 .controller_id = MSM_DP_CONTROLLER_1,
/drivers/gpu/drm/amd/display/dc/hwss/dce112/
A Ddce112_hwseq.c115 uint8_t controller_id, in dce112_enable_display_power_gating() argument
130 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { in dce112_enable_display_power_gating()
133 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating()
139 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), in dce112_enable_display_power_gating()
/drivers/gpu/drm/amd/display/dc/hwss/dce100/
A Ddce100_hwseq.c74 uint8_t controller_id, in dce100_enable_display_power_gating() argument
89 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){ in dce100_enable_display_power_gating()
92 dcb, controller_id + 1, cntl); in dce100_enable_display_power_gating()
98 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id), in dce100_enable_display_power_gating()
/drivers/gpu/drm/amd/display/dc/
A Ddc_bios_types.h102 enum controller_id id,
125 enum controller_id controller_id,
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dabm.h42 bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst);
50 unsigned int controller_id,
/drivers/scsi/aic94xx/
A Daic94xx_sds.h66 struct controller_id { struct
85 struct controller_id contrl_id; /*PCI id to identify the controller */ argument

Completed in 51 milliseconds

1234