| /drivers/mmc/host/ |
| A D | cqhci-core.c | 43 return cq_host->desc_base + (tag * cq_host->slot_sz); in get_desc() 204 cq_host->slot_sz = cq_host->task_desc_len + cq_host->link_desc_len; in cqhci_host_alloc_tdl() 206 cq_host->desc_size = cq_host->slot_sz * cq_host->num_slots; in cqhci_host_alloc_tdl() 208 cq_host->data_size = get_trans_desc_offset(cq_host, cq_host->mmc->cqe_qdepth); in cqhci_host_alloc_tdl() 211 mmc_hostname(cq_host->mmc), cq_host->desc_size, cq_host->data_size, in cqhci_host_alloc_tdl() 241 mmc_hostname(cq_host->mmc), cq_host->desc_base, cq_host->trans_desc_base, in cqhci_host_alloc_tdl() 282 cqhci_writel(cq_host, cq_host->rca, CQHCI_SSC2); in __cqhci_enable() 323 if (cq_host->enabled && cq_host->activated) in cqhci_deactivate() 861 if (cq_host->waiting_for_idle && !cq_host->qcnt) { in cqhci_irq() 885 is_idle = !cq_host->qcnt || cq_host->recovery_halt; in cqhci_is_idle() [all …]
|
| A D | cqhci-crypto.c | 61 cq_host->crypto_cap_array; in cqhci_crypto_keyslot_program() 94 cqhci_crypto_program_key(cq_host, &cfg, slot); in cqhci_crypto_keyslot_program() 108 cqhci_crypto_program_key(cq_host, &cfg, slot); in cqhci_crypto_clear_keyslot() 163 struct mmc_host *mmc = cq_host->mmc; in cqhci_crypto_init() 178 cq_host->crypto_capabilities.reg_val = in cqhci_crypto_init() 181 cq_host->crypto_cfg_register = in cqhci_crypto_init() 184 cq_host->crypto_cap_array = in cqhci_crypto_init() 187 if (!cq_host->crypto_cap_array) { in cqhci_crypto_init() 216 cpu_to_le32(cqhci_readl(cq_host, in cqhci_crypto_init() 220 cq_host->crypto_cap_array[cap_idx]); in cqhci_crypto_init() [all …]
|
| A D | sdhci-tegra.c | 1186 struct mmc_host *mmc = cq_host->mmc; in tegra_cqhci_writel() 1204 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel() 1217 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel() 1219 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel() 1247 if (!cq_host->activated) { in sdhci_tegra_cqe_enable() 1321 reg = cqhci_readl(cq_host, CQHCI_CFG); in sdhci_tegra_cqe_pre_enable() 1323 cqhci_writel(cq_host, reg, CQHCI_CFG); in sdhci_tegra_cqe_pre_enable() 1332 reg = cqhci_readl(cq_host, CQHCI_CFG); in sdhci_tegra_cqe_post_disable() 1592 struct cqhci_host *cq_host; in sdhci_tegra_add_host() local 1608 sizeof(*cq_host), GFP_KERNEL); in sdhci_tegra_add_host() [all …]
|
| A D | sdhci-brcmstb.c | 322 struct cqhci_host *cq_host; in sdhci_brcmstb_add_host() local 335 cq_host = devm_kzalloc(mmc_dev(host->mmc), in sdhci_brcmstb_add_host() 336 sizeof(*cq_host), GFP_KERNEL); in sdhci_brcmstb_add_host() 337 if (!cq_host) { in sdhci_brcmstb_add_host() 342 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_brcmstb_add_host() 343 cq_host->ops = &sdhci_brcmstb_cqhci_ops; in sdhci_brcmstb_add_host() 348 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_brcmstb_add_host() 351 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_brcmstb_add_host()
|
| A D | sdhci-esdhc-imx.c | 1645 if (cq_host) { in sdhci_esdhc_imx_hwinit() 1646 tmp = cqhci_readl(cq_host, CQHCI_IS); in sdhci_esdhc_imx_hwinit() 1647 cqhci_writel(cq_host, tmp, CQHCI_IS); in sdhci_esdhc_imx_hwinit() 1648 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); in sdhci_esdhc_imx_hwinit() 1715 struct cqhci_host *cq_host = mmc->cqe_private; in esdhc_cqe_enable() local 1754 cqhci_writel(cq_host, 0, CQHCI_CTL); in esdhc_cqe_enable() 1834 struct cqhci_host *cq_host; in sdhci_esdhc_imx_probe() local 1945 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in sdhci_esdhc_imx_probe() 1946 if (!cq_host) { in sdhci_esdhc_imx_probe() 1952 cq_host->ops = &esdhc_cqhci_ops; in sdhci_esdhc_imx_probe() [all …]
|
| A D | sdhci-of-dwcmshc.c | 539 static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, in dwcmshc_set_tran_desc() argument 555 *desc += cq_host->trans_desc_len; in dwcmshc_set_tran_desc() 1250 struct cqhci_host *cq_host; in dwcmshc_cqhci_init() local 1258 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); in dwcmshc_cqhci_init() 1259 if (!cq_host) { in dwcmshc_cqhci_init() 1277 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; in dwcmshc_cqhci_init() 1278 cq_host->ops = &dwcmshc_cqhci_ops; in dwcmshc_cqhci_init() 1284 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in dwcmshc_cqhci_init() 1286 err = cqhci_init(cq_host, host->mmc, dma64); in dwcmshc_cqhci_init() 1302 devm_kfree(&pdev->dev, cq_host); in dwcmshc_cqhci_init()
|
| A D | sdhci-pci-gli.c | 1662 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_pre_enable() local 1665 value = cqhci_readl(cq_host, CQHCI_CFG); in sdhci_gl9763e_cqe_pre_enable() 1667 cqhci_writel(cq_host, value, CQHCI_CFG); in sdhci_gl9763e_cqe_pre_enable() 1697 value = cqhci_readl(cq_host, CQHCI_CFG); in sdhci_gl9763e_cqe_post_disable() 1699 cqhci_writel(cq_host, value, CQHCI_CFG); in sdhci_gl9763e_cqe_post_disable() 1715 struct cqhci_host *cq_host; in gl9763e_add_host() local 1723 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); in gl9763e_add_host() 1724 if (!cq_host) { in gl9763e_add_host() 1730 cq_host->ops = &sdhci_gl9763e_cqhci_ops; in gl9763e_add_host() 1734 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in gl9763e_add_host() [all …]
|
| A D | sdhci_am654.c | 708 struct cqhci_host *cq_host; in sdhci_am654_cqe_add_host() local 710 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), in sdhci_am654_cqe_add_host() 712 if (!cq_host) in sdhci_am654_cqe_add_host() 715 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; in sdhci_am654_cqe_add_host() 716 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; in sdhci_am654_cqe_add_host() 717 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_am654_cqe_add_host() 718 cq_host->ops = &sdhci_am654_cqhci_ops; in sdhci_am654_cqe_add_host() 722 return cqhci_init(cq_host, host->mmc, 1); in sdhci_am654_cqe_add_host()
|
| A D | sdhci-msm.c | 1876 struct cqhci_host *cq_host) in sdhci_msm_ice_init() argument 1927 cap.reg_val = cpu_to_le32(cqhci_readl(cq_host, in sdhci_msm_ice_init() 2005 struct cqhci_host *cq_host) in sdhci_msm_ice_init() argument 2116 struct cqhci_host *cq_host; in sdhci_msm_cqe_add_host() local 2132 cq_host = cqhci_pltfm_init(pdev); in sdhci_msm_cqe_add_host() 2133 if (IS_ERR(cq_host)) { in sdhci_msm_cqe_add_host() 2134 ret = PTR_ERR(cq_host); in sdhci_msm_cqe_add_host() 2140 cq_host->ops = &sdhci_msm_cqhci_ops; in sdhci_msm_cqe_add_host() 2144 ret = sdhci_msm_ice_init(msm_host, cq_host); in sdhci_msm_cqe_add_host() 2148 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_msm_cqe_add_host() [all …]
|
| A D | sdhci-of-arasan.c | 1812 struct cqhci_host *cq_host; in sdhci_arasan_add_host() local 1823 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_arasan_add_host() 1824 sizeof(*cq_host), GFP_KERNEL); in sdhci_arasan_add_host() 1825 if (!cq_host) { in sdhci_arasan_add_host() 1830 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_arasan_add_host() 1831 cq_host->ops = &sdhci_arasan_cqhci_ops; in sdhci_arasan_add_host() 1835 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_arasan_add_host() 1837 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_arasan_add_host()
|
| A D | mtk-sd.c | 523 struct cqhci_host *cq_host; member 2826 reg = cqhci_readl(cq_host, CQHCI_CFG); in msdc_cqe_pre_enable() 2828 cqhci_writel(cq_host, reg, CQHCI_CFG); in msdc_cqe_pre_enable() 2836 reg = cqhci_readl(cq_host, CQHCI_CFG); in msdc_cqe_post_disable() 2838 cqhci_writel(cq_host, reg, CQHCI_CFG); in msdc_cqe_post_disable() 3116 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe() 3117 sizeof(*host->cq_host), in msdc_drv_probe() 3119 if (!host->cq_host) { in msdc_drv_probe() 3124 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe() 3125 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe() [all …]
|
| A D | cqhci.h | 292 void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc, 319 int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
|
| A D | sdhci-pci-core.c | 944 struct cqhci_host *cq_host; in glk_emmc_add_host() local 952 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); in glk_emmc_add_host() 953 if (!cq_host) { in glk_emmc_add_host() 958 cq_host->mmio = host->ioaddr + 0x200; in glk_emmc_add_host() 959 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; in glk_emmc_add_host() 960 cq_host->ops = &glk_cqhci_ops; in glk_emmc_add_host() 964 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in glk_emmc_add_host() 966 ret = cqhci_init(cq_host, host->mmc, dma64); in glk_emmc_add_host()
|