| /drivers/spi/ |
| A D | spi-sh.c | 76 unsigned long cr1; member
201 ss->cr1 &= ~SPI_SH_TBE; in spi_sh_send()
360 unsigned long cr1; in spi_sh_irq() local
363 if (cr1 & SPI_SH_TBE) in spi_sh_irq()
364 ss->cr1 |= SPI_SH_TBE; in spi_sh_irq()
365 if (cr1 & SPI_SH_TBF) in spi_sh_irq()
366 ss->cr1 |= SPI_SH_TBF; in spi_sh_irq()
367 if (cr1 & SPI_SH_RBE) in spi_sh_irq()
368 ss->cr1 |= SPI_SH_RBE; in spi_sh_irq()
369 if (cr1 & SPI_SH_RBF) in spi_sh_irq()
[all …]
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| A D | spi-pxa2xx.c | 62 u32 cr1; member
946 u32 cr1; in pxa2xx_spi_transfer_one() local
999 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pxa2xx_spi_transfer_one()
1008 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1192 chip->cr1 = 0; in setup()
1194 chip->cr1 |= SSCR1_SCFR; in setup()
1195 chip->cr1 |= SSCR1_SCLKDIR; in setup()
1196 chip->cr1 |= SSCR1_SFRMDIR; in setup()
1197 chip->cr1 |= SSCR1_SPH; in setup()
1228 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
[all …]
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| A D | spi-pl022.c | 409 u16 cr1; member
478 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
1716 chip->cr1 = 0; in pl022_setup()
1744 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
1754 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
1767 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
1768 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
1769 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
1771 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
1800 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
[all …]
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| A D | spi-rockchip.c | 539 u32 cr1; in rockchip_spi_config() local
563 cr1 = xfer->len - 1; in rockchip_spi_config()
567 cr1 = xfer->len - 1; in rockchip_spi_config()
571 cr1 = xfer->len / 2 - 1; in rockchip_spi_config()
591 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); in rockchip_spi_config()
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| A D | spi-stm32.c | 882 u32 cr1; in stm32h7_spi_disable() local
888 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
890 if (!(cr1 & STM32H7_SPI_CR1_SPE)) { in stm32h7_spi_disable()
2120 u32 cr1 = 0, cfg2 = 0; in stm32h7_spi_config() local
2137 cr1 |= STM32H7_SPI_CR1_HDDIR | STM32H7_SPI_CR1_MASRX | STM32H7_SPI_CR1_SSI; in stm32h7_spi_config()
2148 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1); in stm32h7_spi_config()
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| /drivers/tty/serial/ |
| A D | stm32-usart.c | 47 .cr1 = 0x0c,
65 .cr1 = 0x00,
88 .cr1 = 0x00,
207 *cr1 |= rs485_deat_dedt; in stm32_usart_config_reg_rs485()
219 *cr1 |= rs485_deat_dedt; in stm32_usart_config_reg_rs485()
234 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
256 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
1226 cr1 |= USART_CR1_M0; in stm32_usart_set_termios()
1228 cr1 |= USART_CR1_M1; in stm32_usart_set_termios()
1265 cr1 |= USART_CR1_PS; in stm32_usart_set_termios()
[all …]
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| A D | fsl_linflexuart.c | 317 unsigned long cr, ier, cr1; in linflex_setup_watermark() local
331 cr1 = LINFLEXD_LINCR1_BF | LINFLEXD_LINCR1_MME in linflex_setup_watermark()
333 writel(cr1, sport->membase + LINCR1); in linflex_setup_watermark()
357 cr1 &= ~(LINFLEXD_LINCR1_INIT); in linflex_setup_watermark()
359 writel(cr1, sport->membase + LINCR1); in linflex_setup_watermark()
407 unsigned long cr, old_cr, cr1; in linflex_set_termios() local
414 cr1 = readl(port->membase + LINCR1); in linflex_set_termios()
415 cr1 |= LINFLEXD_LINCR1_INIT; in linflex_set_termios()
416 writel(cr1, port->membase + LINCR1); in linflex_set_termios()
507 cr1 &= ~(LINFLEXD_LINCR1_INIT); in linflex_set_termios()
[all …]
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| A D | fsl_lpuart.c | 1523 u8 cr1; in lpuart_get_mctrl() local
1526 if (cr1 & UARTCR1_LOOPS) in lpuart_get_mctrl()
1546 u8 cr1; in lpuart_set_mctrl() local
1553 cr1 |= UARTCR1_LOOPS; in lpuart_set_mctrl()
2028 cr1 |= UARTCR1_M; in lpuart_set_termios()
2051 cr1 &= ~UARTCR1_PE; in lpuart_set_termios()
2057 cr1 |= UARTCR1_PE; in lpuart_set_termios()
2059 cr1 |= UARTCR1_M; in lpuart_set_termios()
2061 cr1 |= UARTCR1_PT; in lpuart_set_termios()
2063 cr1 &= ~UARTCR1_PT; in lpuart_set_termios()
[all …]
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| A D | stm32-usart.h | 12 u16 cr1; member
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| /drivers/i2c/busses/ |
| A D | i2c-stm32f4.c | 489 u32 cr1; in stm32f4_i2c_handle_rx_addr() local
506 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
507 cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); in stm32f4_i2c_handle_rx_addr()
508 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
513 cr1 |= STM32F4_I2C_CR1_STOP; in stm32f4_i2c_handle_rx_addr()
515 cr1 |= STM32F4_I2C_CR1_START; in stm32f4_i2c_handle_rx_addr()
516 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
527 cr1 &= ~STM32F4_I2C_CR1_ACK; in stm32f4_i2c_handle_rx_addr()
528 cr1 |= STM32F4_I2C_CR1_POS; in stm32f4_i2c_handle_rx_addr()
542 cr1 |= STM32F4_I2C_CR1_ACK; in stm32f4_i2c_handle_rx_addr()
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| A D | i2c-stm32f7.c | 195 u32 cr1; member
889 u32 cr1, cr2; in stm32f7_i2c_xfer_msg() local
959 cr1 |= STM32F7_I2C_CR1_RXIE; in stm32f7_i2c_xfer_msg()
961 cr1 |= STM32F7_I2C_CR1_TXIE; in stm32f7_i2c_xfer_msg()
989 u32 cr1, cr2; in stm32f7_i2c_smbus_xfer_msg() local
1091 cr1 |= STM32F7_I2C_CR1_PECEN; in stm32f7_i2c_smbus_xfer_msg()
1155 u32 cr1, cr2; in stm32f7_i2c_smbus_rep_start() local
1196 cr1 |= STM32F7_I2C_CR1_RXIE; in stm32f7_i2c_smbus_rep_start()
1223 cr1 |= STM32F7_I2C_CR1_RXIE; in stm32f7_i2c_smbus_rep_start()
2447 u32 cr1; in stm32f7_i2c_regs_restore() local
[all …]
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| /drivers/counter/ |
| A D | stm32-timer-cnt.c | 33 u32 cr1; member
116 u32 cr1, sms; in stm32_count_function_write() local
142 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_count_function_write()
162 u32 cr1; in stm32_count_direction_read() local
164 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_count_direction_read()
203 u32 cr1; in stm32_count_enable_read() local
205 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_count_enable_read()
207 *enable = cr1 & TIM_CR1_CEN; in stm32_count_enable_read()
216 u32 cr1; in stm32_count_enable_write() local
221 if (!(cr1 & TIM_CR1_CEN)) { in stm32_count_enable_write()
[all …]
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| /drivers/input/touchscreen/ |
| A D | mc13783_ts.c | 71 int cr0, cr1; in mc13783_ts_report_sample() local
84 cr1 = (priv->sample[3] >> 12) & 0xfff; in mc13783_ts_report_sample()
88 x0, x1, x2, y0, y1, y2, cr0, cr1); in mc13783_ts_report_sample()
93 cr0 = (cr0 + cr1) / 2; in mc13783_ts_report_sample()
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| /drivers/media/platform/nxp/ |
| A D | imx7-media-csi.c | 324 cr1 |= BIT_RFF_OR_INT; in imx7_csi_hw_enable_irq()
325 cr1 |= BIT_FB1_DMA_DONE_INTEN; in imx7_csi_hw_enable_irq()
326 cr1 |= BIT_FB2_DMA_DONE_INTEN; in imx7_csi_hw_enable_irq()
328 imx7_csi_reg_write(csi, cr1, CSI_CSICR1); in imx7_csi_hw_enable_irq()
335 cr1 &= ~BIT_RFF_OR_INT; in imx7_csi_hw_disable_irq()
336 cr1 &= ~BIT_FB1_DMA_DONE_INTEN; in imx7_csi_hw_disable_irq()
337 cr1 &= ~BIT_FB2_DMA_DONE_INTEN; in imx7_csi_hw_disable_irq()
339 imx7_csi_reg_write(csi, cr1, CSI_CSICR1); in imx7_csi_hw_disable_irq()
373 imx7_csi_reg_write(csi, cr1, CSI_CSICR1); in imx7_csi_rx_fifo_clear()
533 u32 cr1, cr18; in imx7_csi_configure() local
[all …]
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| /drivers/phy/freescale/ |
| A D | phy-fsl-lynx-28g.c | 40 #define LYNX_28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24))) argument
113 u32 rstctl, cr0, cr1; member
198 switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) { in lynx_28g_lane_set_nrate()
484 pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1); in lynx_28g_pll_read_configuration()
489 switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) { in lynx_28g_pll_read_configuration()
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| /drivers/iio/trigger/ |
| A D | stm32-timer-trigger.c | 84 u32 cr1; member
247 u32 psc, arr, cr1; in stm32_tt_read_frequency() local
250 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_tt_read_frequency()
254 if (cr1 & TIM_CR1_CEN) { in stm32_tt_read_frequency()
849 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); in stm32_timer_trigger_suspend()
884 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); in stm32_timer_trigger_resume()
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| /drivers/irqchip/ |
| A D | irq-gic-v5-irs.c | 548 u32 cr0, cr1; in gicv5_irs_init_bases() local
561 cr1 = FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_NO_WRITE_ALLOC) | in gicv5_irs_init_bases()
573 cr1 = FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_WRITE_ALLOC) | in gicv5_irs_init_bases()
586 irs_writel_relaxed(irs_data, cr1, GICV5_IRS_CR1); in gicv5_irs_init_bases()
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| A D | irq-gic-v5-its.c | 1116 u32 cr0, cr1; in gicv5_its_init_bases() local
1147 cr1 = FIELD_PREP(GICV5_ITS_CR1_ITT_RA, GICV5_NO_READ_ALLOC) | in gicv5_its_init_bases()
1153 cr1 = FIELD_PREP(GICV5_ITS_CR1_ITT_RA, GICV5_READ_ALLOC) | in gicv5_its_init_bases()
1160 its_writel_relaxed(its_node, cr1, GICV5_ITS_CR1); in gicv5_its_init_bases()
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| /drivers/net/phy/realtek/ |
| A D | realtek_main.c | 750 u16 cr1, cr2; in rtl8211e_led_hw_control_get() local
760 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index; in rtl8211e_led_hw_control_get()
761 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) { in rtl8211e_led_hw_control_get()
791 u16 cr1 = 0, cr2 = 0; in rtl8211e_led_hw_control_set() local
799 cr1 |= RTL8211E_LEDCR1_ACT_TXRX; in rtl8211e_led_hw_control_set()
802 cr1 <<= RTL8211E_LEDCR1_SHIFT * index; in rtl8211e_led_hw_control_set()
804 RTL8211E_LEDCR1, cr1mask, cr1); in rtl8211e_led_hw_control_set()
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| /drivers/iio/adc/ |
| A D | stm32-dfsdm-adc.c | 509 u32 cr1; in stm32_dfsdm_filter_configure() local
565 cr1 = DFSDM_CR1_RCH(chan->channel); in stm32_dfsdm_filter_configure()
569 cr1 |= DFSDM_CR1_RCONT(1); in stm32_dfsdm_filter_configure()
571 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode); in stm32_dfsdm_filter_configure()
584 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0); in stm32_dfsdm_filter_configure()
594 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode); in stm32_dfsdm_filter_configure()
598 cr1); in stm32_dfsdm_filter_configure()
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| /drivers/mtd/devices/ |
| A D | st_spi_fsm.c | 1393 uint8_t sr1, cr1, dyb; in stfsm_s25fl_config() local
1443 stfsm_read_status(fsm, SPINOR_OP_RDCR, &cr1, 1); in stfsm_s25fl_config()
1446 if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { in stfsm_s25fl_config()
1448 cr1 |= STFSM_S25FL_CONFIG_QE; in stfsm_s25fl_config()
1453 if (cr1 & STFSM_S25FL_CONFIG_QE) { in stfsm_s25fl_config()
1455 cr1 &= ~STFSM_S25FL_CONFIG_QE; in stfsm_s25fl_config()
1462 sta_wr = ((uint16_t)cr1 << 8) | sr1; in stfsm_s25fl_config()
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| /drivers/clk/ |
| A D | clk-si521xx.c | 43 #define SI521XX_OE_MAP(cr1, cr2) (((cr2) << 8) | (cr1)) argument
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| /drivers/gpu/drm/mcde/ |
| A D | mcde_display.c | 636 u32 cr0, cr1; in mcde_configure_fifo() local
642 cr1 = MCDE_CRA1; in mcde_configure_fifo()
647 cr1 = MCDE_CRB1; in mcde_configure_fifo()
703 val = readl(mcde->regs + cr1); in mcde_configure_fifo()
744 writel(val, mcde->regs + cr1); in mcde_configure_fifo()
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| /drivers/clk/renesas/ |
| A D | rcar-gen4-cpg.c | 226 static const struct { u16 cr0, cr1; } pll_cr_offsets[] __initconst = { in cpg_pll_clk_register() member
248 pll_clk->pllcr1_reg = base + pll_cr_offsets[index - 1].cr1; in cpg_pll_clk_register()
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| /drivers/parport/ |
| A D | parport_pc.c | 969 int cr1, cr4, cra, cr23, cr26, cr27; in show_parconfig_smsc37c669() local
981 cr1 = inb(io + 1); in show_parconfig_smsc37c669()
996 cr1, cr4, cra, cr23, cr26, cr27); in show_parconfig_smsc37c669()
1008 (cr1 & 4) ? "yes" : "no"); in show_parconfig_smsc37c669()
1010 (cr1 & 0x08) ? "Standard mode only (SPP)" in show_parconfig_smsc37c669()
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