| /drivers/gpu/drm/ |
| A D | drm_client_modeset.c | 554 struct drm_crtc **crtcs; in drm_client_pick_crtcs() local
568 crtcs = kcalloc(connector_count, sizeof(*crtcs), GFP_KERNEL); in drm_client_pick_crtcs()
569 if (!crtcs) in drm_client_pick_crtcs()
604 crtcs[n] = crtc; in drm_client_pick_crtcs()
605 memcpy(crtcs, best_crtcs, n * sizeof(*crtcs)); in drm_client_pick_crtcs()
610 memcpy(best_crtcs, crtcs, connector_count * sizeof(*crtcs)); in drm_client_pick_crtcs()
614 kfree(crtcs); in drm_client_pick_crtcs()
755 crtcs[i] = crtc; in drm_client_firmware_config()
856 crtcs = kcalloc(connector_count, sizeof(*crtcs), GFP_KERNEL); in drm_client_modeset_probe()
877 memset(crtcs, 0, connector_count * sizeof(*crtcs)); in drm_client_modeset_probe()
[all …]
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| A D | drm_atomic.c | 108 kfree(state->crtcs); in drm_atomic_state_default_release()
135 if (!state->crtcs) in drm_atomic_state_init()
225 state->crtcs[i].state); in drm_atomic_state_default_clear()
227 state->crtcs[i].ptr = NULL; in drm_atomic_state_default_clear()
228 state->crtcs[i].state = NULL; in drm_atomic_state_default_clear()
229 state->crtcs[i].old_state = NULL; in drm_atomic_state_default_clear()
230 state->crtcs[i].new_state = NULL; in drm_atomic_state_default_clear()
232 if (state->crtcs[i].commit) { in drm_atomic_state_default_clear()
234 state->crtcs[i].commit = NULL; in drm_atomic_state_default_clear()
364 state->crtcs[index].state = crtc_state; in drm_atomic_get_crtc_state()
[all …]
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_display.h | 300 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
301 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
316 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
317 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
324 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
325 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
341 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
342 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
350 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
351 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
[all …]
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| /drivers/gpu/drm/renesas/rcar-du/ |
| A D | rcar_du_group.c | 108 rcrtc = rcdu->crtcs; in rcar_du_group_setup_didsr()
117 rcrtc = &rcdu->crtcs[rgrp->index * 2]; in rcar_du_group_setup_didsr()
252 struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; in __rcar_du_group_start_stop()
313 crtc = &rcdu->crtcs[index * 2]; in rcar_du_set_dpad0_vsp1_routing()
357 rcrtc = &rcdu->crtcs[rgrp->index * 2 + i]; in rcar_du_group_set_dpad_levels()
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| A D | rcar_du_vsp.h | 60 unsigned int crtcs);
72 unsigned int crtcs) in rcar_du_vsp_init() argument
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| A D | rcar_du_vsp.c | 465 unsigned int crtcs) in rcar_du_vsp_init() argument
469 unsigned int num_crtcs = hweight32(crtcs); in rcar_du_vsp_init()
515 crtcs, &rcar_du_vsp_plane_funcs, in rcar_du_vsp_init()
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| A D | rcar_du_drv.h | 105 struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS]; member
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| A D | rcar_du_kms.c | 732 rcdu->crtcs[i].vsp = &rcdu->vsps[j]; in rcar_du_vsps_init()
733 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; in rcar_du_vsps_init()
985 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i]; in rcar_du_modeset_init()
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| A D | rcar_du_plane.c | 794 unsigned int crtcs; in rcar_du_planes_init() local
804 crtcs = ((1 << rcdu->num_crtcs) - 1) & (3 << (2 * rgrp->index)); in rcar_du_planes_init()
815 crtcs, &rcar_du_plane_funcs, in rcar_du_planes_init()
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| /drivers/gpu/drm/sun4i/ |
| A D | sun8i_dw_hdmi.c | 68 u32 crtcs = 0; in sun8i_dw_hdmi_find_possible_crtcs() local
82 crtcs |= drm_of_crtc_port_mask(drm, remote_port); in sun8i_dw_hdmi_find_possible_crtcs()
87 crtcs = drm_of_find_possible_crtcs(drm, node); in sun8i_dw_hdmi_find_possible_crtcs()
93 return crtcs; in sun8i_dw_hdmi_find_possible_crtcs()
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| /drivers/gpu/drm/vkms/ |
| A D | vkms_config.h | 25 struct list_head crtcs; member
132 list_for_each_entry((crtc_cfg), &(config)->crtcs, link)
229 return list_count_nodes(&config->crtcs); in vkms_config_get_num_crtcs()
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| A D | vkms_config.c | 26 INIT_LIST_HEAD(&config->crtcs); in vkms_config_create()
119 list_for_each_entry_safe(crtc_cfg, crtc_tmp, &config->crtcs, link) in vkms_config_destroy()
212 n_crtcs = list_count_nodes((struct list_head *)&config->crtcs); in valid_crtc_number()
450 list_add_tail(&crtc_cfg->link, &config->crtcs); in vkms_config_create_crtc()
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| /drivers/gpu/drm/renesas/rz-du/ |
| A D | rzg2l_du_vsp.h | 59 unsigned int crtcs);
67 unsigned int crtcs) in rzg2l_du_vsp_init() argument
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| A D | rzg2l_du_vsp.c | 300 unsigned int crtcs) in rzg2l_du_vsp_init() argument
304 unsigned int num_crtcs = hweight32(crtcs); in rzg2l_du_vsp_init()
331 plane, crtcs, &rzg2l_du_vsp_plane_funcs, in rzg2l_du_vsp_init()
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| A D | rzg2l_du_drv.h | 65 struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS]; member
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| A D | rzg2l_du_kms.c | 377 rcdu->crtcs[i].vsp = &rcdu->vsps[j]; in rzg2l_du_vsps_init()
378 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; in rzg2l_du_vsps_init()
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| /drivers/gpu/drm/radeon/ |
| A D | rs690.c | 253 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust()
256 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust()
599 if (rdev->mode_info.crtcs[0]->base.enabled) in rs690_bandwidth_update()
600 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs690_bandwidth_update()
601 if (rdev->mode_info.crtcs[1]->base.enabled) in rs690_bandwidth_update()
602 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs690_bandwidth_update()
626 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rs690_bandwidth_update()
627 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rs690_bandwidth_update()
629 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); in rs690_bandwidth_update()
630 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); in rs690_bandwidth_update()
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| A D | rv515.c | 1213 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_avivo_update()
1214 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update()
1215 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_avivo_update()
1216 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rv515_bandwidth_avivo_update()
1219 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rv515_bandwidth_avivo_update()
1222 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); in rv515_bandwidth_avivo_update()
1223 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); in rv515_bandwidth_avivo_update()
1255 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_update()
1256 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update()
1257 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_update()
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| A D | rs600.c | 121 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
157 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
911 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
912 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
913 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
914 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
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| /drivers/gpu/drm/tidss/ |
| A D | tidss_irq.c | 67 struct drm_crtc *crtc = tidss->crtcs[id]; in tidss_irq_handler()
117 struct tidss_crtc *tcrtc = to_tidss_crtc(tidss->crtcs[i]); in tidss_irq_install()
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| A D | tidss_drv.h | 27 struct drm_crtc *crtcs[TIDSS_MAX_PORTS]; member
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_vkms.c | 184 adev->mode_info.crtcs[drm_crtc_index(crtc)] = amdgpu_crtc; in amdgpu_vkms_crtc_init()
545 if (adev->mode_info.crtcs[i]) in amdgpu_vkms_sw_fini()
546 hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); in amdgpu_vkms_sw_fini()
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| A D | dce_v6_0.c | 204 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
1139 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1143 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1144 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1146 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1148 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
2547 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2548 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
2550 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v6_0_crtc_disable()
2696 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v6_0_crtc_init()
[all …]
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| /drivers/gpu/drm/arm/display/komeda/ |
| A D | komeda_kms.c | 54 komeda_crtc_handle_event(&kms->crtcs[i], &evts); in komeda_kms_irq_handler()
77 struct komeda_crtc *kcrtc = &kms->crtcs[i]; in komeda_kms_atomic_commit_hw_done()
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| A D | komeda_plane.c | 206 crtc = &kms->crtcs[i]; in get_possible_crtcs()
224 kcrtc = &kms->crtcs[i]; in komeda_set_crtc_plane_mask()
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