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Searched refs:csc (Results 1 – 25 of 65) sorted by relevance

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/drivers/gpu/ipu-v3/
A Dipu-ic-csc.c355 static int calc_csc_coeffs(struct ipu_ic_csc *csc) in calc_csc_coeffs() argument
360 tbl_idx = (QUANT_MAP(csc->in_cs.quant) << 1) | in calc_csc_coeffs()
361 QUANT_MAP(csc->out_cs.quant); in calc_csc_coeffs()
363 if (csc->in_cs.cs == csc->out_cs.cs) { in calc_csc_coeffs()
364 csc->params = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
372 switch (csc->out_cs.enc) { in calc_csc_coeffs()
385 csc->params = *params_tbl[tbl_idx]; in calc_csc_coeffs()
390 int __ipu_ic_calc_csc(struct ipu_ic_csc *csc) in __ipu_ic_calc_csc() argument
392 return calc_csc_coeffs(csc); in __ipu_ic_calc_csc()
396 int ipu_ic_calc_csc(struct ipu_ic_csc *csc, in ipu_ic_calc_csc() argument
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A Dipu-ic.c175 const struct ipu_ic_csc *csc, in init_csc() argument
188 c = (const u16 (*)[3])csc->params.coeff; in init_csc()
189 a = (const u16 *)csc->params.offset; in init_csc()
195 param = ((a[0] & 0x1fe0) >> 5) | (csc->params.scale << 8) | in init_csc()
196 (csc->params.sat << 10); in init_csc()
325 const struct ipu_ic_csc *csc, in ipu_ic_task_init_rsc() argument
359 ic->in_cs = csc->in_cs; in ipu_ic_task_init_rsc()
360 ic->out_cs = csc->out_cs; in ipu_ic_task_init_rsc()
362 ret = init_csc(ic, csc, 0); in ipu_ic_task_init_rsc()
369 const struct ipu_ic_csc *csc, in ipu_ic_task_init() argument
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A Dipu-dp.c273 u32 reg, csc; in ipu_dp_disable_channel() local
283 csc = reg & DP_COM_CONF_CSC_DEF_MASK; in ipu_dp_disable_channel()
285 if (csc == DP_COM_CONF_CSC_DEF_BOTH || csc == DP_COM_CONF_CSC_DEF_BG) in ipu_dp_disable_channel()
/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/
A Dia_css_csc.host.c64 if (!csc) return; in ia_css_cc_dump()
68 csc->m_shift); in ia_css_cc_dump()
71 csc->m00); in ia_css_cc_dump()
74 csc->m01); in ia_css_cc_dump()
77 csc->m02); in ia_css_cc_dump()
80 csc->m10); in ia_css_cc_dump()
83 csc->m11); in ia_css_cc_dump()
86 csc->m12); in ia_css_cc_dump()
89 csc->m20); in ia_css_cc_dump()
92 csc->m21); in ia_css_cc_dump()
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A Dia_css_csc.host.h30 const struct sh_css_isp_csc_params *csc, unsigned int level,
35 const struct sh_css_isp_csc_params *csc,
/drivers/media/platform/ti/vpe/
A Dcsc.c112 struct device *dev = &csc->pdev->dev; in csc_dump_regs()
115 ioread32(csc->base + CSC_##r)) in csc_dump_regs()
249 struct csc_data *csc; in csc_create() local
253 csc = devm_kzalloc(&pdev->dev, sizeof(*csc), GFP_KERNEL); in csc_create()
254 if (!csc) { in csc_create()
259 csc->pdev = pdev; in csc_create()
263 if (csc->res == NULL) { in csc_create()
269 csc->base = devm_ioremap_resource(&pdev->dev, csc->res); in csc_create()
270 if (IS_ERR(csc->base)) in csc_create()
271 return ERR_CAST(csc->base); in csc_create()
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A DMakefile5 obj-$(CONFIG_VIDEO_TI_CSC) += ti-csc.o
10 ti-csc-y := csc.o
A Dcsc.h58 void csc_dump_regs(struct csc_data *csc);
59 void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5);
60 void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0,
/drivers/gpu/drm/i915/display/
A Dintel_color.c180 memset(csc, 0, sizeof(*csc)); in intel_csc_clear()
229 csc->coeff[0] << 16 | csc->coeff[1]); in ilk_update_pipe_csc()
234 csc->coeff[3] << 16 | csc->coeff[4]); in ilk_update_pipe_csc()
239 csc->coeff[6] << 16 | csc->coeff[7]); in ilk_update_pipe_csc()
335 csc->coeff[0] << 16 | csc->coeff[1]); in icl_update_output_csc()
340 csc->coeff[3] << 16 | csc->coeff[4]); in icl_update_output_csc()
345 csc->coeff[6] << 16 | csc->coeff[7]); in icl_update_output_csc()
643 csc->coeff[1] << 16 | csc->coeff[0]); in vlv_load_wgc_csc()
648 csc->coeff[4] << 16 | csc->coeff[3]); in vlv_load_wgc_csc()
653 csc->coeff[7] << 16 | csc->coeff[6]); in vlv_load_wgc_csc()
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A Dintel_crtc_state_dump.c143 const struct intel_csc_matrix *csc) in ilk_dump_csc() argument
148 csc->preoff[0], csc->preoff[1], csc->preoff[2]); in ilk_dump_csc()
152 csc->coeff[3 * i + 0], in ilk_dump_csc()
153 csc->coeff[3 * i + 1], in ilk_dump_csc()
154 csc->coeff[3 * i + 2]); in ilk_dump_csc()
160 csc->postoff[0], csc->postoff[1], csc->postoff[2]); in ilk_dump_csc()
165 const struct intel_csc_matrix *csc) in vlv_dump_csc() argument
171 csc->coeff[3 * i + 0], in vlv_dump_csc()
172 csc->coeff[3 * i + 1], in vlv_dump_csc()
173 csc->coeff[3 * i + 2]); in vlv_dump_csc()
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/drivers/gpu/drm/tidss/
A Dtidss_dispc.c1606 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); in dispc_csc_rgb2yuv_regval()
1618 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); in dispc_csc_cpr_regval()
1619 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); in dispc_csc_cpr_regval()
1620 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); in dispc_csc_cpr_regval()
1621 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); in dispc_csc_cpr_regval()
1641 csc->to_regval(csc, regval); in dispc_k2g_vid_write_csc()
1664 csc->to_regval(csc, regval); in dispc_k3_vid_write_csc()
2660 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); in dispc_k2g_vp_csc_cpr_regval()
2661 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); in dispc_k2g_vp_csc_cpr_regval()
2662 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); in dispc_k2g_vp_csc_cpr_regval()
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/drivers/gpu/drm/msm/disp/mdp4/
A Dmdp4_plane.c160 enum mdp4_pipe pipe, struct csc_cfg *csc) in mdp4_write_csc_config() argument
164 for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) { in mdp4_write_csc_config()
166 csc->matrix[i]); in mdp4_write_csc_config()
169 for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) { in mdp4_write_csc_config()
171 csc->pre_bias[i]); in mdp4_write_csc_config()
174 csc->post_bias[i]); in mdp4_write_csc_config()
177 for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) { in mdp4_write_csc_config()
179 csc->pre_clamp[i]); in mdp4_write_csc_config()
182 csc->post_clamp[i]); in mdp4_write_csc_config()
316 struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB); in mdp4_plane_mode_set() local
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/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_cdm.c175 u32 csc = 0; in dpu_hw_cdm_enable() local
195 csc |= CDM_CSC10_OP_MODE_DST_FMT_YUV; in dpu_hw_cdm_enable()
196 csc &= ~CDM_CSC10_OP_MODE_SRC_FMT_YUV; in dpu_hw_cdm_enable()
197 csc |= CDM_CSC10_OP_MODE_EN; in dpu_hw_cdm_enable()
202 DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc); in dpu_hw_cdm_enable()
/drivers/gpu/drm/vc4/
A Dvc4_hvs.c1425 u32 csc[3][5]; member
1431 .csc = {
1438 .csc = {
1445 .csc = {
1454 .csc = {
1461 .csc = {
1468 .csc = {
1495 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]); in vc6_hvs_hw_init()
1496 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]); in vc6_hvs_hw_init()
1497 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]); in vc6_hvs_hw_init()
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/drivers/pcmcia/
A Di82092.c310 int csc; in i82092aa_interrupt() local
317 csc = indirect_read(i, I365_CSC); in i82092aa_interrupt()
319 if (csc == 0) /* no events on this socket */ in i82092aa_interrupt()
324 if (csc & I365_CSC_DETECT) { in i82092aa_interrupt()
332 if (csc & I365_CSC_STSCHG) in i82092aa_interrupt()
336 if (csc & I365_CSC_BVD1) in i82092aa_interrupt()
338 if (csc & I365_CSC_BVD2) in i82092aa_interrupt()
340 if (csc & I365_CSC_READY) in i82092aa_interrupt()
A Dpd6729.c192 unsigned int csc; in pd6729_interrupt() local
195 csc = indirect_read(&socket[i], I365_CSC); in pd6729_interrupt()
196 if (csc == 0) /* no events on this socket */ in pd6729_interrupt()
202 if (csc & I365_CSC_DETECT) { in pd6729_interrupt()
211 events |= (csc & I365_CSC_STSCHG) in pd6729_interrupt()
215 events |= (csc & I365_CSC_BVD1) in pd6729_interrupt()
217 events |= (csc & I365_CSC_BVD2) in pd6729_interrupt()
219 events |= (csc & I365_CSC_READY) in pd6729_interrupt()
/drivers/staging/media/deprecated/atmel/
A Datmel-sama5d2-isc.c202 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama5d2_config_csc()
204 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama5d2_config_csc()
206 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama5d2_config_csc()
208 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama5d2_config_csc()
210 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama5d2_config_csc()
212 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama5d2_config_csc()
440 isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; in atmel_isc_probe()
A Datmel-sama7g5-isc.c215 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
217 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
219 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
221 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
223 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
225 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
429 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
/drivers/gpu/drm/nouveau/dispnv50/
A Dwndw.c142 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
170 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); in nv50_wndw_flush_set()
427 if (wndw->func->csc && asyh->state.ctm) { in nv50_wndw_atomic_check_lut()
429 wndw->func->csc(wndw, asyw, ctm); in nv50_wndw_atomic_check_lut()
430 asyw->csc.valid = true; in nv50_wndw_atomic_check_lut()
431 asyw->set.csc = true; in nv50_wndw_atomic_check_lut()
433 asyw->csc.valid = false; in nv50_wndw_atomic_check_lut()
434 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
515 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check()
740 asyw->csc = armw->csc; in nv50_wndw_atomic_duplicate_state()
A Dbase907c.c144 u32 *val = &asyw->csc.matrix[j * 4 + i]; in base907c_csc()
181 NVVAL(NV907C, SET_CSC_RED2RED, COEFF, asyw->csc.matrix[0]), in base907c_csc_set()
183 SET_CSC_GRN2RED, &asyw->csc.matrix[1], 11); in base907c_csc_set()
198 .csc = base907c_csc,
/drivers/media/platform/amlogic/c3/isp/
A Dc3-isp-params.c47 struct c3_isp_params_csc csc; member
455 const struct c3_isp_params_csc *csc = &block->csc; in c3_isp_params_cfg_csc() local
466 ISP_CM0_COEF00_01_MTX_00(csc->matrix[0][0])); in c3_isp_params_cfg_csc()
469 ISP_CM0_COEF00_01_MTX_01(csc->matrix[0][1])); in c3_isp_params_cfg_csc()
472 ISP_CM0_COEF02_10_MTX_02(csc->matrix[0][2])); in c3_isp_params_cfg_csc()
476 ISP_CM0_COEF02_10_MTX_10(csc->matrix[1][0])); in c3_isp_params_cfg_csc()
479 ISP_CM0_COEF11_12_MTX_11(csc->matrix[1][1])); in c3_isp_params_cfg_csc()
482 ISP_CM0_COEF11_12_MTX_12(csc->matrix[1][2])); in c3_isp_params_cfg_csc()
486 ISP_CM0_COEF20_21_MTX_20(csc->matrix[2][0])); in c3_isp_params_cfg_csc()
489 ISP_CM0_COEF20_21_MTX_21(csc->matrix[2][1])); in c3_isp_params_cfg_csc()
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/drivers/media/platform/microchip/
A Dmicrochip-sama5d2-isc.c222 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama5d2_config_csc()
224 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama5d2_config_csc()
226 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama5d2_config_csc()
228 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama5d2_config_csc()
230 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama5d2_config_csc()
232 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama5d2_config_csc()
459 isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; in microchip_isc_probe()
A Dmicrochip-sama7g5-isc.c235 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
237 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
239 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
241 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
243 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
245 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
448 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_plane.c495 struct csc_cfg *csc) in csc_enable() argument
500 if (unlikely(!csc)) in csc_enable()
503 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) in csc_enable()
505 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) in csc_enable()
510 matrix = csc->matrix; in csc_enable()
526 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { in csc_enable()
527 uint32_t *pre_clamp = csc->pre_clamp; in csc_enable()
528 uint32_t *post_clamp = csc->post_clamp; in csc_enable()
539 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); in csc_enable()
542 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); in csc_enable()
/drivers/media/platform/ti/omap3isp/
A Disppreview.c400 const struct omap3isp_prev_csc *csc = &params->csc; in preview_config_csc() local
403 val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT; in preview_config_csc()
404 val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT; in preview_config_csc()
405 val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT; in preview_config_csc()
408 val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT; in preview_config_csc()
413 val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT; in preview_config_csc()
418 val = (csc->offset[0] & 0xff) << ISPPRV_CSC_OFFSET_Y_SHIFT; in preview_config_csc()
800 offsetof(struct prev_params, csc),
801 sizeof_field(struct prev_params, csc),
802 offsetof(struct omap3isp_prev_update_config, csc),
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