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Searched refs:csr (Results 1 – 25 of 125) sorted by relevance

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/drivers/crypto/intel/qat/qat_common/
A Dadf_gen4_ras.c55 void __iomem *csr) in enable_ae_error_reporting() argument
76 void __iomem *csr) in enable_cpp_error_reporting() argument
168 void __iomem *csr) in enable_rf_error_reporting() argument
247 void __iomem *csr) in disable_ssm_error_reporting() argument
351 void __iomem *csr) in adf_gen4_process_errsou0() argument
781 void __iomem *csr) in adf_handle_spp_pulldata_err() argument
925 void __iomem *csr) in adf_handle_spp_pushdata_err() argument
1112 void __iomem *csr) in adf_handle_iaintstatssm() argument
1136 void __iomem *csr) in adf_handle_exprpssmcmpr() argument
1155 void __iomem *csr) in adf_handle_exprpssmxlt() argument
[all …]
A Dadf_gen6_ras.c13 ADF_CSR_WR(csr, ADF_GEN6_ERRMSK0, 0); in enable_errsou_reporting()
16 ADF_CSR_WR(csr, ADF_GEN6_ERRMSK1, 0); in enable_errsou_reporting()
25 ADF_CSR_WR(csr, ADF_GEN6_ERRMSK3, 0); in enable_errsou_reporting()
95 void __iomem *csr) in enable_ssm_error_reporting() argument
105 enable_errsou_reporting(csr); in adf_gen6_enable_ras()
108 enable_ti_ri_error_reporting(csr); in adf_gen6_enable_ras()
195 disable_errsou_reporting(csr); in adf_gen6_disable_ras()
196 disable_ae_error_reporting(csr); in adf_gen6_disable_ras()
197 disable_cpp_error_reporting(csr); in adf_gen6_disable_ras()
198 disable_ti_ri_error_reporting(csr); in adf_gen6_disable_ras()
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A Dicp_qat_hw_20_comp.h27 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
39 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
42 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
96 QAT_FIELD_SET(val32, csr.lbms, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER()
125 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER()
137 QAT_FIELD_SET(val32, csr.lbc, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER()
154 QAT_FIELD_SET(val32, csr.sdc, in ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER()
[all …]
A Dicp_qat_hw_51_comp.h20 ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_51_config_csr_lower csr) in ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER() argument
24 QAT_FIELD_SET(val32, csr.abd, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER()
27 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.lbc, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER()
54 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_UPPER()
57 QAT_FIELD_SET(val32, csr.bms, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_UPPER()
60 QAT_FIELD_SET(val32, csr.scb_mode_reset, in ICP_QAT_FW_COMP_51_BUILD_CONFIG_UPPER()
76 QAT_FIELD_SET(val32, csr.lbc, in ICP_QAT_FW_DECOMP_51_BUILD_CONFIG_LOWER()
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A Dicp_qat_hal.h125 #define SET_CAP_CSR(handle, csr, val) \ argument
126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
127 #define GET_CAP_CSR(handle, csr) \ argument
128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
A Dadf_gen4_hw_data.c91 void __iomem *csr = misc_bar->virt_addr; in adf_gen4_enable_error_correction() local
117 u32 csr; in adf_gen4_init_device() local
123 csr = ADF_CSR_RD(addr, ADF_GEN4_ERRMSK2); in adf_gen4_init_device()
124 csr |= ADF_GEN4_PM_SOU; in adf_gen4_init_device()
125 ADF_CSR_WR(addr, ADF_GEN4_ERRMSK2, csr); in adf_gen4_init_device()
171 void __iomem *csr; in adf_gen4_set_msix_default_rttable() local
203 csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); in reset_ring_pair()
216 void __iomem *csr = adf_get_etr_base(accel_dev); in adf_gen4_ring_pair_reset() local
225 ret = reset_ring_pair(csr, bank_number); in adf_gen4_ring_pair_reset()
465 csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); in drain_bank()
[all …]
A Dadf_hw_arbiter.c21 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local
36 WRITE_CSR_ARB_SARCONFIG(csr, arb_off, arb, arb_cfg); in adf_init_arb()
42 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, thd_2_arb_cfg[i]); in adf_init_arb()
79 void __iomem *csr; in adf_exit_arb() local
89 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
95 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, 0); in adf_exit_arb()
99 csr_ops->write_csr_ring_srv_arb_en(csr, i, 0); in adf_exit_arb()
105 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_disable_arb_thd() local
123 WRITE_CSR_ARB_WT2SAM(csr, info.arb_offset, info.wt2sam_offset, ae, in adf_disable_arb_thd()
/drivers/usb/musb/
A Dmusb_gadget.c230 u16 fifo_count = 0, csr; in txstate() local
269 csr); in txstate()
389 csr |= MUSB_TXCSR_TXPKTRDY; in txstate()
409 u16 csr; in musb_g_tx() local
793 u16 csr; in musb_g_rx() local
919 u16 csr; in musb_gadget_enable() local
1003 csr |= MUSB_TXCSR_P_ISO; in musb_gadget_enable()
1043 csr |= MUSB_RXCSR_P_ISO; in musb_gadget_enable()
1165 u16 csr; in musb_ep_restart() local
1335 u16 csr; in musb_gadget_set_halt() local
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A Dmusb_gadget_ep0.c243 u16 csr; in service_zero_data_request() local
403 u16 csr; in service_zero_data_request() local
465 u16 count, csr; in ep0_rxstate() local
490 csr |= MUSB_CSR0_P_DATAEND; in ep0_rxstate()
501 musb->ackpend = csr; in ep0_rxstate()
546 csr |= MUSB_CSR0_P_DATAEND; in ep0_txstate()
556 musb->ackpend = csr; in ep0_txstate()
643 u16 csr; in musb_g_ep0_irq() local
843 handled, csr, in musb_g_ep0_irq()
997 u16 csr; in musb_g_ep0_halt() local
[all …]
A Dmusb_host.c91 u16 csr; in musb_h_tx_flush_fifo() local
125 u16 csr; in musb_h_ep0_flush_fifo() local
418 u16 csr; in musb_host_packet_rx() local
518 u16 csr; in musb_rx_reinit() local
580 u16 csr; in musb_tx_dma_set_mode_mentor() local
653 u16 csr; in musb_tx_dma_program() local
683 u16 csr; in musb_ep_program() local
722 u16 csr; in musb_ep_program() local
840 u16 csr = 0; in musb_ep_program() local
1057 u16 csr, len; in musb_h_ep0_irq() local
[all …]
A Dmusb_cppi41.c56 u16 csr; in save_rx_toggle() local
74 u16 csr; in update_rx_toggle() local
105 u16 csr; in musb_is_tx_fifo_empty() local
108 csr = musb_readw(epio, MUSB_TXCSR); in musb_is_tx_fifo_empty()
109 if (csr & MUSB_TXCSR_TXPKTRDY) in musb_is_tx_fifo_empty()
122 u16 csr; in cppi41_trans_done() local
179 csr |= MUSB_RXCSR_H_REQPKT; in cppi41_trans_done()
582 u16 csr; in cppi41_dma_channel_abort() local
593 csr &= ~MUSB_TXCSR_DMAENAB; in cppi41_dma_channel_abort()
610 csr |= MUSB_RXCSR_FLUSHFIFO; in cppi41_dma_channel_abort()
[all …]
A Dmusbhsdma.c152 u16 csr = 0; in configure_channel() local
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
178 csr); in configure_channel()
228 u16 csr; in dma_channel_abort() local
239 csr = musb_readw(mbase, offset); in dma_channel_abort()
241 musb_writew(mbase, offset, csr); in dma_channel_abort()
242 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort()
243 musb_writew(mbase, offset, csr); in dma_channel_abort()
249 csr &= ~(MUSB_RXCSR_AUTOCLEAR | in dma_channel_abort()
283 u16 csr; in dma_controller_irq() local
[all …]
/drivers/crypto/starfive/
A Djh7110-rsa.c82 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
90 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
97 rctx->csr.pka.ie = 1; in starfive_rsa_montgomery_form()
112 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
118 rctx->csr.pka.ie = 1; in starfive_rsa_montgomery_form()
125 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
132 rctx->csr.pka.ie = 1; in starfive_rsa_montgomery_form()
146 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
152 rctx->csr.pka.ie = 1; in starfive_rsa_montgomery_form()
199 rctx->csr.pka.v = 0; in starfive_rsa_cpu_start()
[all …]
/drivers/scsi/
A Dsun3_scsi.c196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
243 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
270 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
348 unsigned short csr; in sun3scsi_dma_start() local
350 csr = dregs->csr; in sun3scsi_dma_start()
474 dregs->csr |= CSR_FIFO; in sun3scsi_dma_finish()
549 oldcsr = dregs->csr; in sun3_scsi_probe()
550 dregs->csr = 0; in sun3_scsi_probe()
555 dregs->csr = oldcsr; in sun3_scsi_probe()
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A Dsun3x_esp.c86 u32 csr; in sun3x_esp_dma_drain() local
89 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain()
90 if (!(csr & DMA_FIFO_ISDRAIN)) in sun3x_esp_dma_drain()
131 u32 csr; in sun3x_esp_send_dma_cmd() local
137 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd()
138 csr |= DMA_ENABLE; in sun3x_esp_send_dma_cmd()
140 csr |= DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
142 csr &= ~DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
143 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd()
151 u32 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_error() local
[all …]
A Dsun_esp.c323 u32 csr; in sbus_esp_dma_drain() local
329 csr = dma_read32(DMA_CSR); in sbus_esp_dma_drain()
389 u32 csr; in sbus_esp_send_dma_cmd() local
404 csr |= DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
406 csr &= ~DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
411 dma_write32(csr, DMA_CSR); in sbus_esp_send_dma_cmd()
413 csr = dma_read32(DMA_CSR); in sbus_esp_send_dma_cmd()
414 csr |= DMA_ENABLE; in sbus_esp_send_dma_cmd()
416 csr |= DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
418 csr &= ~DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
[all …]
/drivers/watchdog/
A Dshwdt.c85 u8 csr; in sh_wdt_start() local
97 sh_wdt_write_csr(csr); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
116 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
128 u8 csr; in sh_wdt_stop() local
135 csr &= ~WTCSR_TME; in sh_wdt_stop()
136 sh_wdt_write_csr(csr); in sh_wdt_stop()
181 u8 csr; in sh_wdt_ping() local
[all …]
/drivers/usb/gadget/udc/
A Dat91_udc.c112 u32 csr; in proc_ep_show() local
133 csr, in proc_ep_show()
140 (!(csr & 0x700)) in proc_ep_show()
315 u32 csr; in read_fifo() local
342 csr |= CLR_FX; in read_fifo()
408 csr |= CLR_FX; in write_fifo()
442 csr &= ~SET_FX; in write_fifo()
742 u32 csr; in at91_ep_set_halt() local
762 csr |= CLR_FX; in at91_ep_set_halt()
1074 csr |= CLR_FX; in handle_setup()
[all …]
/drivers/net/pcs/
A Dpcs-xpcs-plat.c43 return FIELD_GET(0x1fff00, csr); in xpcs_mmio_addr_page()
48 return FIELD_GET(0xff, csr); in xpcs_mmio_addr_offset()
54 ptrdiff_t csr, ofs; in xpcs_mmio_read_reg_indirect() local
58 csr = xpcs_mmio_addr_format(dev, reg); in xpcs_mmio_read_reg_indirect()
59 page = xpcs_mmio_addr_page(csr); in xpcs_mmio_read_reg_indirect()
60 ofs = xpcs_mmio_addr_offset(csr); in xpcs_mmio_read_reg_indirect()
85 ptrdiff_t csr, ofs; in xpcs_mmio_write_reg_indirect() local
90 page = xpcs_mmio_addr_page(csr); in xpcs_mmio_write_reg_indirect()
91 ofs = xpcs_mmio_addr_offset(csr); in xpcs_mmio_write_reg_indirect()
116 ptrdiff_t csr; in xpcs_mmio_read_reg_direct() local
[all …]
/drivers/dma/
A Dtegra186-gpc-dma.c189 u32 csr; member
457 u32 csr, status; in tegra_dma_disable() local
465 csr &= ~TEGRA_GPCDMA_CSR_ENB; in tegra_dma_disable()
669 u32 status, csr; in tegra_dma_stop_client() local
842 u32 *csr, in get_transfer_param() argument
876 u32 csr, mc_seq; in tegra_dma_prep_dma_memset() local
926 sg_req[0].ch_regs.csr = csr; in tegra_dma_prep_dma_memset()
943 u32 csr, mc_seq; in tegra_dma_prep_dma_memcpy() local
996 sg_req[0].ch_regs.csr = csr; in tegra_dma_prep_dma_memcpy()
1115 sg_req[i].ch_regs.csr = csr; in tegra_dma_prep_slave_sg()
[all …]
/drivers/pcmcia/
A Dpxa2xx_sharpsl.c57 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local
65 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state()
66 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state()
74 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state()
90 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state()
91 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state()
92 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state()
93 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state()
94 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state()
95 state->vs_3v = (csr & 0x0040) ? 0 : 1; in sharpsl_pcmcia_socket_state()
[all …]
/drivers/usb/mtu3/
A Dmtu3_gadget_ep0.c139 u32 csr; in ep0_stall_set() local
144 csr |= EP0_SENDSTALL | pktrdy; in ep0_stall_set()
146 csr = (csr & ~EP0_SENDSTALL) | EP0_SENTSTALL; in ep0_stall_set()
515 u32 csr; in ep0_rx_state() local
537 csr |= EP0_RXPKTRDY; in ep0_rx_state()
545 csr |= EP0_DATAEND; in ep0_rx_state()
567 u32 csr; in ep0_tx_state() local
607 u32 csr; in ep0_read_setup() local
702 u32 csr; in mtu3_ep0_isr() local
722 if (csr & EP0_SENTSTALL) { in mtu3_ep0_isr()
[all …]
/drivers/net/wireless/ath/wil6210/
A Dinterrupt.c297 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
359 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx_edma()
410 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx_edma()
456 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
544 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
687 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
690 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
695 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
698 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
704 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
[all …]
/drivers/power/reset/
A Dxgene-reboot.c25 void __iomem *csr; member
34 writel(ctx->mask, ctx->csr); in xgene_restart_handler()
53 ctx->csr = devm_platform_ioremap_resource(pdev, 0); in xgene_reboot_probe()
54 if (IS_ERR(ctx->csr)) { in xgene_reboot_probe()
56 return PTR_ERR(ctx->csr); in xgene_reboot_probe()
/drivers/crypto/intel/qat/qat_6xxx/
A Dadf_6xxx_hw_data.c357 void __iomem *csr = adf_get_pmisc_base(accel_dev); in enable_error_correction() local
407 void __iomem *csr = adf_get_pmisc_base(accel_dev); in set_msix_default_rttable() local
432 csr, ADF_WQM_CSR_RPRESETSTS(bank_number)); in reset_ring_pair()
445 void __iomem *csr = adf_get_etr_base(accel_dev); in ring_pair_reset() local
453 ret = reset_ring_pair(csr, bank_number); in ring_pair_reset()
623 void __iomem *csr = adf_get_etr_base(accel_dev); in adf_gen6_set_vc() local
628 set_vc_csr_for_bank(csr, i); in adf_gen6_set_vc()
782 u32 csr; in adf_init_device() local
786 csr = ADF_CSR_RD(addr, ADF_GEN6_ERRMSK2); in adf_init_device()
787 csr |= ADF_GEN6_PM_SOU; in adf_init_device()
[all …]

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