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Searched refs:csr_base_addr (Results 1 – 5 of 5) sorted by relevance

/drivers/crypto/intel/qat/qat_common/
A Dadf_gen4_hw_csr_data.h45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
54 #define READ_CSR_NE_STAT(csr_base_addr, bank) \ argument
57 #define READ_CSR_NF_STAT(csr_base_addr, bank) \ argument
60 #define READ_CSR_F_STAT(csr_base_addr, bank) \ argument
63 #define READ_CSR_C_STAT(csr_base_addr, bank) \ argument
66 #define READ_CSR_EXP_STAT(csr_base_addr, bank) \ argument
86 void __iomem *_csr_base_addr = csr_base_addr; \
128 #define READ_CSR_INT_EN(csr_base_addr, bank) \ argument
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A Dadf_gen4_hw_csr_data.c35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
40 return READ_CSR_UO_STAT(csr_base_addr, bank); in read_csr_uo_stat()
45 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
50 return READ_CSR_NE_STAT(csr_base_addr, bank); in read_csr_ne_stat()
55 return READ_CSR_NF_STAT(csr_base_addr, bank); in read_csr_nf_stat()
60 return READ_CSR_F_STAT(csr_base_addr, bank); in read_csr_f_stat()
65 return READ_CSR_C_STAT(csr_base_addr, bank); in read_csr_c_stat()
70 return READ_CSR_EXP_STAT(csr_base_addr, bank); in read_csr_exp_stat()
110 return READ_CSR_INT_EN(csr_base_addr, bank); in read_csr_int_en()
115 WRITE_CSR_INT_EN(csr_base_addr, bank, value); in write_csr_int_en()
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A Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
59 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
62 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ argument
69 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
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A Dadf_gen2_hw_csr_data.c13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
47 WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr); in write_csr_ring_base()
52 WRITE_CSR_INT_FLAG(csr_base_addr, bank, value); in write_csr_int_flag()
57 WRITE_CSR_INT_SRCSEL(csr_base_addr, bank); in write_csr_int_srcsel()
63 WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value); in write_csr_int_col_en()
69 WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value); in write_csr_int_col_ctl()
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A Dadf_accel_devices.h172 u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);
173 u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);
174 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
175 u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);
176 u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);
177 u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u32 bank);
178 u32 (*read_csr_c_stat)(void __iomem *csr_base_addr, u32 bank);
191 u32 (*read_csr_int_en)(void __iomem *csr_base_addr, u32 bank);
192 void (*write_csr_int_en)(void __iomem *csr_base_addr, u32 bank,
199 void (*write_csr_int_srcsel_w_val)(void __iomem *csr_base_addr,
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