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Searched refs:cstate (Results 1 – 25 of 45) sorted by relevance

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/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
A Dhal_bt_coexist.c25 rtlpriv->btcoexist.cstate &= in _rtl8723_dm_bt_check_wifi_state()
29 rtlpriv->btcoexist.cstate |= in _rtl8723_dm_bt_check_wifi_state()
32 rtlpriv->btcoexist.cstate &= in _rtl8723_dm_bt_check_wifi_state()
36 rtlpriv->btcoexist.cstate |= in _rtl8723_dm_bt_check_wifi_state()
39 rtlpriv->btcoexist.cstate &= in _rtl8723_dm_bt_check_wifi_state()
43 rtlpriv->btcoexist.cstate &= in _rtl8723_dm_bt_check_wifi_state()
45 rtlpriv->btcoexist.cstate &= in _rtl8723_dm_bt_check_wifi_state()
51 rtlpriv->btcoexist.cstate |= in _rtl8723_dm_bt_check_wifi_state()
53 rtlpriv->btcoexist.cstate &= in _rtl8723_dm_bt_check_wifi_state()
55 rtlpriv->btcoexist.cstate &= in _rtl8723_dm_bt_check_wifi_state()
[all …]
A Dhal_btc.c25 rtlpriv->btcoexist.cstate = 0; in rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps()
117 rtlpriv->btcoexist.cstate |= in rtl8723e_dm_bt_need_to_dec_bt_pwr()
131 rtlpriv->btcoexist.cstate) && in rtl8723e_dm_bt_is_same_coexist_state()
346 rtlpriv->btcoexist.cstate |= in rtl8723e_dm_bt_is_2_ant_common_action()
1366 rtlpriv->btcoexist.cstate |= in rtl8723e_dm_bt_inq_page_monitor()
1384 rtlpriv->btcoexist.cstate &= in rtl8723e_dm_bt_inq_page_monitor()
1394 rtlpriv->btcoexist.cstate &= ~ in rtl8723e_dm_bt_reset_action_profile_state()
1398 rtlpriv->btcoexist.cstate &= ~ in rtl8723e_dm_bt_reset_action_profile_state()
1434 rtlpriv->btcoexist.cstate |= in _rtl8723e_dm_bt_coexist_2_ant()
1637 rtlpriv->btcoexist.cstate); in rtl8723e_dm_bt_coexist_8723()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dbase.c119 if (!pstate || !cstate) in nvkm_cstate_find_best()
123 return cstate; in nvkm_cstate_find_best()
138 return cstate; in nvkm_cstate_find_best()
153 return cstate; in nvkm_cstate_get()
171 cstate = nvkm_cstate_find_best(clk, pstate, cstate); in nvkm_cstate_prog()
172 if (!cstate) in nvkm_cstate_prog()
221 kfree(cstate); in nvkm_cstate_del()
242 cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); in nvkm_cstate_new()
243 if (!cstate) in nvkm_cstate_new()
246 *cstate = pstate->base; in nvkm_cstate_new()
[all …]
A Dgf100.c277 u32 freq = cstate->domain[dom]; in calc_clk()
294 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
325 gf100_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) in gf100_clk_calc() argument
330 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || in gf100_clk_calc()
331 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || in gf100_clk_calc()
332 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || in gf100_clk_calc()
333 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || in gf100_clk_calc()
334 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || in gf100_clk_calc()
335 (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) || in gf100_clk_calc()
336 (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) || in gf100_clk_calc()
[all …]
A Dgt215.c274 calc_clk(struct gt215_clk *clk, struct nvkm_cstate *cstate, in calc_clk() argument
277 int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom], in calc_clk()
285 calc_host(struct gt215_clk *clk, struct nvkm_cstate *cstate) in calc_host() argument
288 u32 kHz = cstate->domain[nv_clk_src_host]; in calc_host()
459 gt215_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) in gt215_clk_calc() argument
465 if ((ret = calc_clk(clk, cstate, 0x10, 0x4200, nv_clk_src_core)) || in gt215_clk_calc()
466 (ret = calc_clk(clk, cstate, 0x11, 0x4220, nv_clk_src_shader)) || in gt215_clk_calc()
467 (ret = calc_clk(clk, cstate, 0x20, 0x0000, nv_clk_src_disp)) || in gt215_clk_calc()
468 (ret = calc_clk(clk, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || in gt215_clk_calc()
469 (ret = calc_host(clk, cstate))) in gt215_clk_calc()
[all …]
A Dgk104.c288 struct nvkm_cstate *cstate, int idx, int dom) in calc_clk() argument
291 u32 freq = cstate->domain[dom]; in calc_clk()
308 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
339 gk104_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) in gk104_clk_calc() argument
344 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || in gk104_clk_calc()
345 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || in gk104_clk_calc()
346 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || in gk104_clk_calc()
347 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || in gk104_clk_calc()
348 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || in gk104_clk_calc()
349 (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) || in gk104_clk_calc()
[all …]
A Dnv40.c146 nv40_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) in nv40_clk_calc() argument
149 int gclk = cstate->domain[nv_clk_src_core]; in nv40_clk_calc()
150 int sclk = cstate->domain[nv_clk_src_shader]; in nv40_clk_calc()
A Dnv50.c369 nv50_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) in nv50_clk_calc() argument
375 const int shader = cstate->domain[nv_clk_src_shader]; in nv50_clk_calc()
376 const int core = cstate->domain[nv_clk_src_core]; in nv50_clk_calc()
377 const int vdec = cstate->domain[nv_clk_src_vdec]; in nv50_clk_calc()
378 const int dom6 = cstate->domain[nv_clk_src_dom6]; in nv50_clk_calc()
A Dmcp77.c200 mcp77_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) in mcp77_clk_calc() argument
203 const int shader = cstate->domain[nv_clk_src_shader]; in mcp77_clk_calc()
204 const int core = cstate->domain[nv_clk_src_core]; in mcp77_clk_calc()
205 const int vdec = cstate->domain[nv_clk_src_vdec]; in mcp77_clk_calc()
/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_crtc.c899 struct dpu_crtc_state *cstate; in dpu_crtc_atomic_flush() local
964 kfree(cstate); in dpu_crtc_destroy_state()
1094 struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); in dpu_crtc_reset() local
1099 if (cstate) in dpu_crtc_reset()
1114 if (!cstate) { in dpu_crtc_duplicate_state()
1122 return &cstate->base; in dpu_crtc_duplicate_state()
1205 cstate->bw_control = false; in dpu_crtc_disable()
1424 cstate->num_mixers = num_lm; in dpu_crtc_assign_resources()
1492 memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); in dpu_crtc_atomic_check()
1498 if (cstate->num_mixers) { in dpu_crtc_atomic_check()
[all …]
/drivers/staging/media/atomisp/pci/
A Datomisp_trace_event.h77 TP_PROTO(int cstate),
79 TP_ARGS(cstate),
82 __field(int, cstate)
86 __entry->cstate = cstate;
89 TP_printk("cstate=%d", __entry->cstate)
/drivers/idle/
A Dintel_idle.c1688 if (cstate + 1 > max_cstate) { in intel_idle_max_cstate_reached()
1734 int cstate, limit; in intel_idle_cst_usable() local
1739 for (cstate = 1; cstate < limit; cstate++) { in intel_idle_cst_usable()
1791 for (cstate = 1; cstate < limit; cstate++) { in intel_idle_init_cstates_acpi()
1798 cx = &acpi_state_table.states[cstate]; in intel_idle_init_cstates_acpi()
1822 if (disabled_states_mask & BIT(cstate)) in intel_idle_init_cstates_acpi()
1839 int cstate, limit; in intel_idle_off_by_default() local
1853 for (cstate = 1; cstate < limit; cstate++) { in intel_idle_off_by_default()
2159 int cstate; in intel_idle_init_cstates_icpu() local
2190 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { in intel_idle_init_cstates_icpu()
[all …]
/drivers/gpu/drm/tidss/
A Dtidss_kms.c53 struct drm_crtc_state *cstate; in tidss_atomic_check() local
77 cstate = drm_atomic_get_crtc_state(state, in tidss_atomic_check()
79 if (IS_ERR(cstate)) in tidss_atomic_check()
80 return PTR_ERR(cstate); in tidss_atomic_check()
81 to_tidss_crtc_state(cstate)->plane_pos_changed = true; in tidss_atomic_check()
85 for_each_new_crtc_in_state(state, crtc, cstate, i) { in tidss_atomic_check()
86 if (to_tidss_crtc_state(cstate)->plane_pos_changed || in tidss_atomic_check()
87 cstate->zpos_changed) { in tidss_atomic_check()
A Dtidss_crtc.c126 struct drm_crtc_state *cstate = crtc->state; in tidss_crtc_position_planes() local
129 if (!newmodeset && !cstate->zpos_changed && in tidss_crtc_position_planes()
130 !to_tidss_crtc_state(cstate)->plane_pos_changed) in tidss_crtc_position_planes()
/drivers/net/slip/
A Dslhc.c95 struct cstate *ts; in slhc_init()
106 size_t rsize = rslots * sizeof(struct cstate); in slhc_init()
114 size_t tsize = tslots * sizeof(struct cstate); in slhc_init()
230 struct cstate *ocs = &(comp->tstate[comp->xmit_oldest]); in slhc_compress()
231 struct cstate *lcs = ocs; in slhc_compress()
232 struct cstate *cs = lcs->next; in slhc_compress()
499 struct cstate *cs; in slhc_uncompress()
649 struct cstate *cs; in slhc_remember()
/drivers/pwm/
A Dpwm-stm32-lp.c127 struct pwm_state cstate; in stm32_pwm_lp_apply() local
132 pwm_get_state(pwm, &cstate); in stm32_pwm_lp_apply()
133 reenable = !cstate.enabled; in stm32_pwm_lp_apply()
136 if (cstate.enabled) { in stm32_pwm_lp_apply()
206 if (!cstate.enabled) { in stm32_pwm_lp_apply()
288 if (!cstate.enabled) in stm32_pwm_lp_apply()
A Dpwm-sun4i.c234 struct pwm_state cstate; in sun4i_pwm_apply() local
240 pwm_get_state(pwm, &cstate); in sun4i_pwm_apply()
242 if (!cstate.enabled) { in sun4i_pwm_apply()
254 if (!cstate.enabled) in sun4i_pwm_apply()
300 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC); in sun4i_pwm_apply()
A Dpwm-sprd.c168 struct pwm_state *cstate = &pwm->state; in sprd_pwm_apply() local
175 if (!cstate->enabled) { in sprd_pwm_apply()
196 } else if (cstate->enabled) { in sprd_pwm_apply()
/drivers/gpu/drm/tve200/
A Dtve200_display.c73 struct drm_crtc_state *cstate) in tve200_display_check() argument
75 const struct drm_display_mode *mode = &cstate->mode; in tve200_display_check()
115 cstate->mode_changed = true; in tve200_display_check()
122 struct drm_crtc_state *cstate, in tve200_display_enable() argument
129 const struct drm_display_mode *mode = &cstate->mode; in tve200_display_enable()
/drivers/gpu/drm/nouveau/nvkm/engine/device/
A Dctrl.c76 struct nvkm_cstate *cstate; in nvkm_control_mthd_pstate_attr() local
113 list_for_each_entry(cstate, &pstate->list, head) { in nvkm_control_mthd_pstate_attr()
114 lo = min(lo, cstate->domain[domain->name]); in nvkm_control_mthd_pstate_attr()
115 hi = max(hi, cstate->domain[domain->name]); in nvkm_control_mthd_pstate_attr()
/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
A Dbase.c137 if (therm->cstate) { in nvkm_therm_update()
138 duty = therm->cstate; in nvkm_therm_update()
167 if (!dir || (dir < 0 && fan < therm->cstate) || in nvkm_therm_cstate()
168 (dir > 0 && fan > therm->cstate)) { in nvkm_therm_cstate()
170 therm->cstate = fan; in nvkm_therm_cstate()
/drivers/gpu/drm/pl111/
A Dpl111_display.c87 struct drm_crtc_state *cstate) in pl111_display_check() argument
89 const struct drm_display_mode *mode = &cstate->mode; in pl111_display_check()
113 cstate->mode_changed = true; in pl111_display_check()
120 struct drm_crtc_state *cstate, in pl111_display_enable() argument
127 const struct drm_display_mode *mode = &cstate->mode; in pl111_display_enable()
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_encoder.c206 struct drm_crtc_state *cstate = encoder->crtc->state; in mdp5_encoder_enable() local
208 mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode); in mdp5_encoder_enable()
/drivers/gpu/drm/atmel-hlcdc/
A Datmel_hlcdc_crtc.c419 struct drm_connector_state *cstate; in atmel_hlcdc_crtc_select_output_mode() local
428 for_each_new_connector_in_state(state->state, connector, cstate, i) { in atmel_hlcdc_crtc_select_output_mode()
431 if (!cstate->crtc) in atmel_hlcdc_crtc_select_output_mode()
434 supported_fmts = atmel_hlcdc_connector_output_mode(cstate); in atmel_hlcdc_crtc_select_output_mode()
/drivers/block/drbd/
A Ddrbd_state_change.h20 enum drbd_conns cstate[2]; /* drbd9: enum drbd_conn_state */ member

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