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Searched refs:ct (Results 1 – 25 of 130) sorted by relevance

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/drivers/gpu/drm/xe/
A Dxe_guc_ct.c118 return container_of(ct, struct xe_guc, ct); in ct_to_guc()
647 CT_DEAD(ct, &ct->ctbs.g2h, G2H_RELEASE); in __g2h_release_space()
811 CT_DEAD(ct, &ct->ctbs.h2g, H2G_WRITE); in h2g_write()
947 (desc_read(ct_to_xe(ct), (&ct->ctbs.g2h), tail) != ct->ctbs.g2h.info.head) in guc_ct_send_locked()
968 CT_DEAD(ct, &ct->ctbs.h2g, DEADLOCK); in guc_ct_send_locked()
1600 CT_DEAD(ct, &ct->ctbs.g2h, G2H_READ); in g2h_read()
1655 len = g2h_read(ct, ct->fast_msg, true); in xe_guc_ct_fast_path()
1657 g2h_fast_path(ct, ct->fast_msg, len); in xe_guc_ct_fast_path()
1674 len = g2h_read(ct, ct->msg, false); in dequeue_one_g2h()
1679 ret = parse_g2h_msg(ct, ct->msg, len); in dequeue_one_g2h()
[all …]
A Dxe_guc_ct.h14 int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct);
15 int xe_guc_ct_init(struct xe_guc_ct *ct);
16 int xe_guc_ct_enable(struct xe_guc_ct *ct);
17 void xe_guc_ct_disable(struct xe_guc_ct *ct);
18 void xe_guc_ct_stop(struct xe_guc_ct *ct);
19 void xe_guc_ct_fast_path(struct xe_guc_ct *ct);
35 return ct->state == XE_GUC_CT_STATE_ENABLED; in xe_guc_ct_enabled()
40 if (!xe_guc_ct_enabled(ct)) in xe_guc_ct_irq_handler()
43 wake_up_all(&ct->wq); in xe_guc_ct_irq_handler()
44 queue_work(ct->g2h_wq, &ct->g2h_worker); in xe_guc_ct_irq_handler()
[all …]
/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_ct.c42 return container_of(ct, struct intel_guc, ct); in ct_to_guc()
321 memset(ct, 0, sizeof(*ct)); in intel_guc_ct_fini()
374 ct->enabled = true; in intel_guc_ct_enable()
385 CT_DEAD(ct, SETUP); in intel_guc_ct_enable()
583 CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); in ct_deadlocked()
584 CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); in ct_deadlocked()
587 CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); in ct_deadlocked()
588 CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); in ct_deadlocked()
998 CT_DEAD(ct, READ); in ct_read()
1339 struct intel_guc_ct *ct = from_tasklet(ct, t, receive_tasklet); in ct_receive_tasklet_func() local
[all …]
A Dintel_guc_ct.h109 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
110 int intel_guc_ct_init(struct intel_guc_ct *ct);
111 void intel_guc_ct_fini(struct intel_guc_ct *ct);
112 int intel_guc_ct_enable(struct intel_guc_ct *ct);
113 void intel_guc_ct_disable(struct intel_guc_ct *ct);
115 static inline void intel_guc_ct_sanitize(struct intel_guc_ct *ct) in intel_guc_ct_sanitize() argument
117 ct->enabled = false; in intel_guc_ct_sanitize()
120 static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct) in intel_guc_ct_enabled() argument
122 return ct->enabled; in intel_guc_ct_enabled()
133 int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
[all …]
/drivers/video/fbdev/aty/
A Dmach64_ct.c266 …ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / … in aty_pll_to_var_ct()
268 if(pll->ct.xres > 0) { in aty_pll_to_var_ct()
270 ret /= pll->ct.xres; in aty_pll_to_var_ct()
293 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl); in aty_set_pll_ct()
298 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real); in aty_set_pll_ct()
411 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07; in aty_init_pll_ct()
434 __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div); in aty_init_pll_ct()
487 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay) in aty_init_pll_ct()
488 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1; in aty_init_pll_ct()
540 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8; in aty_init_pll_ct()
[all …]
/drivers/macintosh/
A Dwindfarm.h30 s32 (*get_min)(struct wf_control *ct);
31 s32 (*get_max)(struct wf_control *ct);
32 void (*release)(struct wf_control *ct);
63 s32 vmax = ct->ops->get_max(ct); in wf_control_set_max()
64 return ct->ops->set_value(ct, vmax); in wf_control_set_max()
69 s32 vmin = ct->ops->get_min(ct); in wf_control_set_min()
70 return ct->ops->set_value(ct, vmin); in wf_control_set_min()
75 return ct->ops->set_value(ct, val); in wf_control_set()
80 return ct->ops->get_value(ct, val); in wf_control_get()
85 return ct->ops->get_min(ct); in wf_control_get_min()
[all …]
A Dwindfarm_core.c153 if (ct->ops && ct->ops->release) in wf_control_release()
154 ct->ops->release(ct); in wf_control_release()
156 kfree(ct); in wf_control_release()
209 struct wf_control *ct; in wf_register_control() local
213 if (!strcmp(ct->name, new_ct->name)) { in wf_register_control()
245 list_del(&ct->link); in wf_unregister_control()
256 if (!try_module_get(ct->ops->owner)) in wf_get_control()
258 kref_get(&ct->ref); in wf_get_control()
265 struct module *mod = ct->ops->owner; in wf_put_control()
374 struct wf_control *ct; in wf_register_client() local
[all …]
A Dwindfarm_pm112.c275 struct wf_control *ct; in cpu_fans_tick() local
333 ct = cpu_fans[i]; in cpu_fans_tick()
334 if (ct == NULL) in cpu_fans_tick()
336 err = ct->ops->set_value(ct, target * cpu_fan_scale[i] / 100); in cpu_fans_tick()
563 if (wf_get_control(ct) == 0) in pm112_new_control()
564 cpufreq_clamp = ct; in pm112_new_control()
570 cpu_fans[i] = ct; in pm112_new_control()
578 backside_fan = ct; in pm112_new_control()
581 slots_fan = ct; in pm112_new_control()
584 drive_bay_fan = ct; in pm112_new_control()
[all …]
A Dwindfarm_pm91.c544 if (wf_get_control(ct) == 0) in wf_smu_new_control()
545 fan_cpu_main = ct; in wf_smu_new_control()
549 if (wf_get_control(ct) == 0) in wf_smu_new_control()
550 fan_cpu_second = ct; in wf_smu_new_control()
554 if (wf_get_control(ct) == 0) in wf_smu_new_control()
555 fan_cpu_third = ct; in wf_smu_new_control()
559 if (wf_get_control(ct) == 0) in wf_smu_new_control()
560 cpufreq_clamp = ct; in wf_smu_new_control()
564 if (wf_get_control(ct) == 0) in wf_smu_new_control()
565 fan_hd = ct; in wf_smu_new_control()
[all …]
A Dwindfarm_pm72.c675 cpu_front_fans[0] = ct; in pm72_new_control()
677 cpu_front_fans[1] = ct; in pm72_new_control()
679 cpu_rear_fans[0] = ct; in pm72_new_control()
681 cpu_rear_fans[1] = ct; in pm72_new_control()
683 cpu_pumps[0] = ct; in pm72_new_control()
685 cpu_pumps[1] = ct; in pm72_new_control()
687 backside_fan = ct; in pm72_new_control()
688 else if (!strcmp(ct->name, "slots-fan")) in pm72_new_control()
689 slots_fan = ct; in pm72_new_control()
691 drives_fan = ct; in pm72_new_control()
[all …]
A Dwindfarm_rm31.c571 if (!strcmp(ct->name, "cpu-fan-a-0")) in rm31_new_control()
572 cpu_fans[0][0] = ct; in rm31_new_control()
574 cpu_fans[0][1] = ct; in rm31_new_control()
576 cpu_fans[0][2] = ct; in rm31_new_control()
578 cpu_fans[1][0] = ct; in rm31_new_control()
580 cpu_fans[1][1] = ct; in rm31_new_control()
582 cpu_fans[1][2] = ct; in rm31_new_control()
584 backside_fan = ct; in rm31_new_control()
585 else if (!strcmp(ct->name, "slots-fan")) in rm31_new_control()
586 slots_fan = ct; in rm31_new_control()
[all …]
A Dwindfarm_smu_controls.c109 static void smu_fan_release(struct wf_control *ct) in smu_fan_release() argument
111 struct smu_fan_control *fct = to_smu_fan(ct); in smu_fan_release()
116 static int smu_fan_set(struct wf_control *ct, s32 value) in smu_fan_set() argument
118 struct smu_fan_control *fct = to_smu_fan(ct); in smu_fan_set()
129 static int smu_fan_get(struct wf_control *ct, s32 *value) in smu_fan_get() argument
131 struct smu_fan_control *fct = to_smu_fan(ct); in smu_fan_get()
136 static s32 smu_fan_min(struct wf_control *ct) in smu_fan_min() argument
138 struct smu_fan_control *fct = to_smu_fan(ct); in smu_fan_min()
142 static s32 smu_fan_max(struct wf_control *ct) in smu_fan_max() argument
144 struct smu_fan_control *fct = to_smu_fan(ct); in smu_fan_max()
/drivers/irqchip/
A Dirq-brcmstb-l2.c130 if (ct->chip.irq_ack) { in brcmstb_l2_intc_resume()
133 ct->regs.ack); in brcmstb_l2_intc_resume()
149 struct irq_chip_type *ct; in brcmstb_l2_intc_of_init() local
216 ct = data->gc->chip_types; in brcmstb_l2_intc_of_init()
219 ct->regs.ack = init_params->cpu_clear; in brcmstb_l2_intc_of_init()
220 ct->chip.irq_ack = irq_gc_ack_set_bit; in brcmstb_l2_intc_of_init()
227 ct->chip.irq_mask = irq_gc_mask_disable_reg; in brcmstb_l2_intc_of_init()
228 ct->regs.disable = init_params->cpu_mask_set; in brcmstb_l2_intc_of_init()
229 ct->regs.mask = init_params->cpu_mask_status; in brcmstb_l2_intc_of_init()
235 ct->chip.irq_resume = brcmstb_l2_intc_resume; in brcmstb_l2_intc_of_init()
[all …]
A Dirq-ingenic-tcu.c56 regmap_write(map, ct->regs.ack, mask); in ingenic_tcu_gc_unmask_enable_reg()
57 regmap_write(map, ct->regs.enable, mask); in ingenic_tcu_gc_unmask_enable_reg()
58 *ct->mask_cache |= mask; in ingenic_tcu_gc_unmask_enable_reg()
69 regmap_write(map, ct->regs.disable, mask); in ingenic_tcu_gc_mask_disable_reg()
70 *ct->mask_cache &= ~mask; in ingenic_tcu_gc_mask_disable_reg()
81 regmap_write(map, ct->regs.ack, mask); in ingenic_tcu_gc_mask_disable_reg_and_ack()
89 struct irq_chip_type *ct; in ingenic_tcu_irq_init() local
130 ct = gc->chip_types; in ingenic_tcu_irq_init()
135 ct->regs.disable = TCU_REG_TMSR; in ingenic_tcu_irq_init()
136 ct->regs.enable = TCU_REG_TMCR; in ingenic_tcu_irq_init()
[all …]
A Dirq-ls1x.c107 struct irq_chip_type *ct; in ls1x_intc_of_init() local
159 ct = gc->chip_types; in ls1x_intc_of_init()
160 ct[0].type = IRQ_TYPE_LEVEL_MASK; in ls1x_intc_of_init()
161 ct[0].regs.mask = LS_REG_INTC_EN; in ls1x_intc_of_init()
162 ct[0].regs.ack = LS_REG_INTC_CLR; in ls1x_intc_of_init()
165 ct[0].chip.irq_ack = irq_gc_ack_set_bit; in ls1x_intc_of_init()
167 ct[0].handler = handle_level_irq; in ls1x_intc_of_init()
169 ct[1].type = IRQ_TYPE_EDGE_BOTH; in ls1x_intc_of_init()
170 ct[1].regs.mask = LS_REG_INTC_EN; in ls1x_intc_of_init()
171 ct[1].regs.ack = LS_REG_INTC_CLR; in ls1x_intc_of_init()
[all …]
A Dirq-omap-intc.c202 struct irq_chip_type *ct; in omap_alloc_gc_of() local
206 ct = gc->chip_types; in omap_alloc_gc_of()
208 ct->type = IRQ_TYPE_LEVEL_MASK; in omap_alloc_gc_of()
210 ct->chip.irq_ack = omap_mask_ack_irq; in omap_alloc_gc_of()
214 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; in omap_alloc_gc_of()
227 struct irq_chip_type *ct; in omap_alloc_gc_legacy() local
231 ct = gc->chip_types; in omap_alloc_gc_legacy()
232 ct->chip.irq_ack = omap_mask_ack_irq; in omap_alloc_gc_legacy()
235 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; in omap_alloc_gc_legacy()
237 ct->regs.enable = INTC_MIR_CLEAR0; in omap_alloc_gc_legacy()
[all …]
A Dirq-ingenic.c65 struct irq_chip_type *ct; in ingenic_intc_of_init() local
114 ct = gc->chip_types; in ingenic_intc_of_init()
115 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; in ingenic_intc_of_init()
116 ct->regs.disable = JZ_REG_INTC_SET_MASK; in ingenic_intc_of_init()
117 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in ingenic_intc_of_init()
118 ct->chip.irq_mask = irq_gc_mask_disable_reg; in ingenic_intc_of_init()
119 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; in ingenic_intc_of_init()
120 ct->chip.irq_set_wake = irq_gc_set_wake; in ingenic_intc_of_init()
121 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; in ingenic_intc_of_init()
A Dirq-bcm7120-l2.c86 struct irq_chip_type *ct = gc->chip_types; in bcm7120_l2_intc_suspend() local
95 struct irq_chip_type *ct = gc->chip_types; in bcm7120_l2_intc_resume() local
99 irq_reg_writel(gc, gc->mask_cache, ct->regs.mask); in bcm7120_l2_intc_resume()
221 struct irq_chip_type *ct; in bcm7120_l2_intc_probe() local
291 ct = gc->chip_types; in bcm7120_l2_intc_probe()
294 ct->regs.mask = data->en_offset[idx]; in bcm7120_l2_intc_probe()
300 ct->chip.irq_mask = irq_gc_mask_clr_bit; in bcm7120_l2_intc_probe()
301 ct->chip.irq_unmask = irq_gc_mask_set_bit; in bcm7120_l2_intc_probe()
302 ct->chip.irq_ack = irq_gc_noop; in bcm7120_l2_intc_probe()
311 gc->mask_cache = irq_reg_readl(gc, ct->regs.mask); in bcm7120_l2_intc_probe()
[all …]
A Dirq-goldfish-pic.c60 struct irq_chip_type *ct; in goldfish_pic_of_init() local
95 ct = gc->chip_types; in goldfish_pic_of_init()
96 ct->regs.enable = GFPIC_REG_IRQ_ENABLE; in goldfish_pic_of_init()
97 ct->regs.disable = GFPIC_REG_IRQ_DISABLE; in goldfish_pic_of_init()
98 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in goldfish_pic_of_init()
99 ct->chip.irq_mask = irq_gc_mask_disable_reg; in goldfish_pic_of_init()
/drivers/gpio/
A Dgpio-mxs.c74 if (!(ct->type & type)) in mxs_gpio_set_irq_type()
189 struct irq_chip_type *ct; in mxs_gpio_init_gc() local
199 ct = &gc->chip_types[0]; in mxs_gpio_init_gc()
201 ct->chip.irq_ack = irq_gc_ack_set_bit; in mxs_gpio_init_gc()
202 ct->chip.irq_mask = irq_gc_mask_disable_reg; in mxs_gpio_init_gc()
206 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; in mxs_gpio_init_gc()
211 ct = &gc->chip_types[1]; in mxs_gpio_init_gc()
213 ct->chip.irq_ack = irq_gc_ack_set_bit; in mxs_gpio_init_gc()
214 ct->chip.irq_mask = irq_gc_mask_disable_reg; in mxs_gpio_init_gc()
218 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; in mxs_gpio_init_gc()
[all …]
A Dgpio-sodaville.c128 struct irq_chip_type *ct; in sdv_register_irqsupport() local
159 ct = sd->gc->chip_types; in sdv_register_irqsupport()
160 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in sdv_register_irqsupport()
161 ct->regs.eoi = GPSTR; in sdv_register_irqsupport()
162 ct->regs.mask = GPIO_INT; in sdv_register_irqsupport()
163 ct->chip.irq_mask = irq_gc_mask_clr_bit; in sdv_register_irqsupport()
164 ct->chip.irq_unmask = irq_gc_mask_set_bit; in sdv_register_irqsupport()
165 ct->chip.irq_eoi = irq_gc_eoi; in sdv_register_irqsupport()
166 ct->chip.irq_set_type = sdv_gpio_pub_set_type; in sdv_register_irqsupport()
A Dgpio-mvebu.c423 ct->mask_cache_priv &= ~mask; in mvebu_gpio_edge_irq_mask()
436 ct->mask_cache_priv |= mask; in mvebu_gpio_edge_irq_unmask()
448 ct->mask_cache_priv &= ~mask; in mvebu_gpio_level_irq_mask()
460 ct->mask_cache_priv |= mask; in mvebu_gpio_level_irq_unmask()
509 if (!(ct->type & type)) in mvebu_gpio_irq_set_type()
1123 struct irq_chip_type *ct; in mvebu_gpio_probe() local
1267 ct = &gc->chip_types[0]; in mvebu_gpio_probe()
1272 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1274 ct = &gc->chip_types[1]; in mvebu_gpio_probe()
1280 ct->handler = handle_edge_irq; in mvebu_gpio_probe()
[all …]
/drivers/scsi/libfc/
A Dfc_encode.h69 struct fc_ct_req *ct; in fc_ct_hdr_fill() local
74 memset(ct, 0, ct_plen); in fc_ct_hdr_fill()
75 ct->hdr.ct_rev = FC_CT_REV; in fc_ct_hdr_fill()
76 ct->hdr.ct_fs_type = fs_type; in fc_ct_hdr_fill()
77 ct->hdr.ct_fs_subtype = subtype; in fc_ct_hdr_fill()
78 ct->hdr.ct_cmd = htons((u16) op); in fc_ct_hdr_fill()
79 return ct; in fc_ct_hdr_fill()
96 struct fc_ct_req *ct; in fc_ct_ns_fill() local
144 memcpy(ct->payload.spn.fr_name, in fc_ct_ns_fill()
155 memcpy(ct->payload.snn.fr_name, in fc_ct_ns_fill()
[all …]
/drivers/scsi/elx/libefc/
A Defc_els.c899 } *ct; in efc_ns_send_rftid() local
911 els->io.iparam.ct.df_ctl = 0; in efc_ns_send_rftid()
916 ct = els->io.req.virt; in efc_ns_send_rftid()
917 memset(ct, 0, sizeof(*ct)); in efc_ns_send_rftid()
936 } *ct; in efc_ns_send_rffid() local
952 ct = els->io.req.virt; in efc_ns_send_rffid()
954 memset(ct, 0, sizeof(*ct)); in efc_ns_send_rffid()
976 } *ct; in efc_ns_send_gidpt() local
993 ct = els->io.req.virt; in efc_ns_send_gidpt()
995 memset(ct, 0, sizeof(*ct)); in efc_ns_send_gidpt()
[all …]
/drivers/crypto/nx/
A Dnx-common-powernv.c691 vas_init_tx_win_attr(&txattr, coproc->ct); in nx_alloc_txwin()
755 coproc->ct = high; in nx_set_ct()
757 coproc->ct = normal; in nx_set_ct()
767 int vasid, int type, int *ct) in vas_cfg_coproc_info() argument
862 *ct = pid; in vas_cfg_coproc_info()
894 int *ct) in find_nx_device_tree() argument
955 unsigned int ct, ci; in nx842_powernv_probe() local
978 coproc->ct = ct; in nx842_powernv_probe()
985 nx842_ct = ct; in nx842_powernv_probe()
986 else if (nx842_ct != ct) in nx842_powernv_probe()
[all …]

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