Searched refs:ctl_val (Results 1 – 7 of 7) sorted by relevance
68 u32 ctl_val[ASPEED_SPI_MAX]; member303 u32 ctl_val; in do_aspeed_spi_exec_op() local309 ctl_val = chip->ctl_val[ASPEED_SPI_BASE]; in do_aspeed_spi_exec_op()310 ctl_val &= ~CTRL_IO_CMD_MASK; in do_aspeed_spi_exec_op()338 writel(ctl_val, chip->ctl); in do_aspeed_spi_exec_op()554 u32 ctl_val; in aspeed_spi_dirmap_create() local604 chip->ctl_val[ASPEED_SPI_READ] = ctl_val; in aspeed_spi_dirmap_create()961 u32 ctl_val; in aspeed_spi_do_calibration() local973 ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask; in aspeed_spi_do_calibration()974 writel(ctl_val, chip->ctl); in aspeed_spi_do_calibration()[all …]
95 int ctl_val, cur_val; in bcm_kona_show() local105 ctl_val = secure_register_read(wdt, SECWDOG_CTRL_REG); in bcm_kona_show()109 if (ctl_val < 0 || cur_val < 0) { in bcm_kona_show()114 ctl = ctl_val & SECWDOG_COUNT_MASK; in bcm_kona_show()115 res = (ctl_val & SECWDOG_RES_MASK) >> SECWDOG_CLKS_SHIFT; in bcm_kona_show()
225 u32 ctl_val; in switchtec_ntb_mw_clr_direct() local228 ctl_val &= ~NTB_CTRL_BAR_DIR_WIN_EN; in switchtec_ntb_mw_clr_direct()248 u32 ctl_val; in switchtec_ntb_mw_set_direct() local251 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN; in switchtec_ntb_mw_set_direct()916 u32 ctl_val; in config_rsvd_lut_win() local925 ctl_val &= 0xFF; in config_rsvd_lut_win()926 ctl_val |= NTB_CTRL_BAR_LUT_WIN_EN; in config_rsvd_lut_win()927 ctl_val |= ilog2(LUT_SIZE) << 8; in config_rsvd_lut_win()928 ctl_val |= (sndev->nr_lut_mw - 1) << 14; in config_rsvd_lut_win()1005 u32 ctl_val; in crosslink_setup_mws() local[all …]
294 u32 ctl_val; in spm_set_low_power_mode() local298 ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); in spm_set_low_power_mode()299 ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT); in spm_set_low_power_mode()300 ctl_val |= start_index << SPM_CTL_INDEX_SHIFT; in spm_set_low_power_mode()301 ctl_val |= SPM_CTL_EN; in spm_set_low_power_mode()302 spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); in spm_set_low_power_mode()
143 u32 ctl_val = 0; in cxd2880_tnrdmd_dvbt_mon_carrier_offset() local183 ctl_val = in cxd2880_tnrdmd_dvbt_mon_carrier_offset()186 *offset = cxd2880_convert2s_complement(ctl_val, 29); in cxd2880_tnrdmd_dvbt_mon_carrier_offset()
85 u32 ctl_val = 0; in cxd2880_tnrdmd_dvbt2_mon_carrier_offset() local136 ctl_val = in cxd2880_tnrdmd_dvbt2_mon_carrier_offset()139 *offset = cxd2880_convert2s_complement(ctl_val, 28); in cxd2880_tnrdmd_dvbt2_mon_carrier_offset()
2767 u8 *ctl_val = ee->ee_ctl; in ath5k_get_max_ctl_power() local2798 if (ctl_val[i] == ctl_mode) { in ath5k_get_max_ctl_power()
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