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Searched refs:ctrl2 (Results 1 – 25 of 40) sorted by relevance

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/drivers/rtc/
A Drtc-rx8025.c134 int ctrl2; in rx8025_check_validity() local
138 if (ctrl2 < 0) in rx8025_check_validity()
139 return ctrl2; in rx8025_check_validity()
163 if (ctrl2 < 0) in rx8025_reset_validity()
164 return ctrl2; in rx8025_reset_validity()
174 ctrl2); in rx8025_reset_validity()
284 u8 ctrl[2], ctrl2; in rx8025_init_client() local
305 ctrl2 = ctrl[1]; in rx8025_init_client()
331 int ctrl2, err; in rx8025_read_alarm() local
338 if (ctrl2 < 0) in rx8025_read_alarm()
[all …]
A Drtc-rs5c372.c231 if (ctrl2 & RS5C_CTRL2_XSTP) { in rs5c372_rtc_read_time()
264 unsigned char ctrl2; in rs5c372_rtc_set_time() local
289 ctrl2 = i2c_smbus_read_byte_data(client, addr); in rs5c372_rtc_set_time()
295 ctrl2 &= ~(R2x2x_CTRL2_VDET | R2x2x_CTRL2_PON); in rs5c372_rtc_set_time()
297 ctrl2 |= R2x2x_CTRL2_XSTP; in rs5c372_rtc_set_time()
299 ctrl2 &= ~R2x2x_CTRL2_XSTP; in rs5c372_rtc_set_time()
302 ctrl2 &= ~RS5C_CTRL2_XSTP; in rs5c372_rtc_set_time()
498 unsigned char ctrl2; in rs5c372_ioctl() local
518 if (ctrl2 & R2x2x_CTRL2_VDET) in rs5c372_ioctl()
522 if (ctrl2 & RS5C_CTRL2_XSTP) in rs5c372_ioctl()
[all …]
A Drtc-rc5t619.c123 unsigned int ctrl2; in rc5t619_rtc_read_time() local
125 err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, &ctrl2); in rc5t619_rtc_read_time()
129 if (ctrl2 & CTRL2_PON) in rc5t619_rtc_read_time()
169 unsigned int ctrl2; in rc5t619_rtc_set_time() local
171 err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, &ctrl2); in rc5t619_rtc_set_time()
175 if (ctrl2 & CTRL2_PON) in rc5t619_rtc_set_time()
355 unsigned int ctrl2; in rc5t619_rtc_probe() local
374 err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, &ctrl2); in rc5t619_rtc_probe()
383 if (ctrl2 & CTRL2_PON) { in rc5t619_rtc_probe()
A Drtc-pcf2127.c617 unsigned int ctrl2; in pcf2127_rtc_read_alarm() local
620 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); in pcf2127_rtc_read_alarm()
633 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; in pcf2127_rtc_read_alarm()
634 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; in pcf2127_rtc_read_alarm()
750 unsigned int ctrl2; in pcf2127_rtc_irq() local
753 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); in pcf2127_rtc_irq()
775 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) in pcf2127_rtc_irq()
777 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); in pcf2127_rtc_irq()
804 if (ctrl2 & PCF2131_CTRL2_IRQ_MASK) in pcf2127_rtc_irq()
806 ctrl2 & ~PCF2131_CTRL2_IRQ_MASK); in pcf2127_rtc_irq()
[all …]
/drivers/comedi/drivers/
A Dme_daq.c168 devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA; in me_dio_insn_config()
170 devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA; in me_dio_insn_config()
172 devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA; in me_dio_insn_config()
174 devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA; in me_dio_insn_config()
176 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_dio_insn_config()
251 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
257 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
306 devpriv->ctrl2 |= ME_CTRL2_DAC_ENA; in me_ao_insn_write()
307 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
310 devpriv->ctrl2 |= ME_CTRL2_BUFFERED_DAC; in me_ao_insn_write()
[all …]
/drivers/pci/
A Dvc.c107 u32 ctrl, header, cap1, ctrl2; in pci_vc_enable() local
140 pci_read_config_dword(dev->bus->self, ctrl_pos2, &ctrl2); in pci_vc_enable()
141 if ((ctrl2 & PCI_VC_RES_CTRL_ID) == id) { in pci_vc_enable()
151 if (ctrl2 & PCI_VC_RES_CTRL_ENABLE) { in pci_vc_enable()
152 ctrl2 &= ~PCI_VC_RES_CTRL_ENABLE; in pci_vc_enable()
153 pci_write_config_dword(link, ctrl_pos2, ctrl2); in pci_vc_enable()
157 ctrl2 |= PCI_VC_RES_CTRL_ENABLE; in pci_vc_enable()
158 pci_write_config_dword(link, ctrl_pos2, ctrl2); in pci_vc_enable()
/drivers/media/platform/renesas/vsp1/
A Dvsp1_sru.c42 u32 ctrl2; member
57 .ctrl2 = VI6_SRU_CTRL2_PARAMS(24, 40, 255),
60 .ctrl2 = VI6_SRU_CTRL2_PARAMS(8, 16, 255),
63 .ctrl2 = VI6_SRU_CTRL2_PARAMS(36, 60, 255),
66 .ctrl2 = VI6_SRU_CTRL2_PARAMS(12, 27, 255),
69 .ctrl2 = VI6_SRU_CTRL2_PARAMS(48, 80, 255),
72 .ctrl2 = VI6_SRU_CTRL2_PARAMS(16, 36, 255),
304 vsp1_sru_write(sru, dlb, VI6_SRU_CTRL2, param->ctrl2); in sru_configure_stream()
/drivers/crypto/bcm/
A Dspu2.c446 static void spu2_dump_fmd_ctrl2(u64 ctrl2) in spu2_dump_fmd_ctrl2() argument
448 packet_log(" FMD CTRL2 %#16llx\n", ctrl2); in spu2_dump_fmd_ctrl2()
451 ctrl2 & SPU2_AAD1_OFFSET, in spu2_dump_fmd_ctrl2()
452 (ctrl2 & SPU2_AAD1_LEN) >> SPU2_AAD1_LEN_SHIFT); in spu2_dump_fmd_ctrl2()
473 spu2_dump_fmd_ctrl2(le64_to_cpu(fmd->ctrl2)); in spu2_dump_fmd()
562 u64 ctrl2; in spu2_fmd_init() local
583 ctrl2 = aad1_offset | in spu2_fmd_init()
592 fmd->ctrl2 = cpu_to_le64(ctrl2); in spu2_fmd_init()
737 u64 ctrl2; in spu2_fmd_ctrl2_write() local
748 ctrl2 = aad1_offset | in spu2_fmd_ctrl2_write()
[all …]
/drivers/net/phy/
A Dphy-c45.c112 int bt1_ctrl, ctrl1, ctrl2, ret; in genphy_c45_pma_setup_forced() local
123 if (ctrl2 < 0) in genphy_c45_pma_setup_forced()
124 return ctrl2; in genphy_c45_pma_setup_forced()
131 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); in genphy_c45_pma_setup_forced()
136 ctrl2 |= MDIO_PMA_CTRL2_BASET1; in genphy_c45_pma_setup_forced()
138 ctrl2 |= MDIO_PMA_CTRL2_10BT; in genphy_c45_pma_setup_forced()
142 ctrl2 |= MDIO_PMA_CTRL2_100BTX; in genphy_c45_pma_setup_forced()
147 ctrl2 |= MDIO_PMA_CTRL2_1000BT; in genphy_c45_pma_setup_forced()
152 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; in genphy_c45_pma_setup_forced()
157 ctrl2 |= MDIO_PMA_CTRL2_5GBT; in genphy_c45_pma_setup_forced()
[all …]
A Ddp83822.c433 int ctrl2; in dp83822_read_status() local
441 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); in dp83822_read_status()
442 if (ctrl2 < 0) in dp83822_read_status()
443 return ctrl2; in dp83822_read_status()
445 if (!(ctrl2 & DP83822_FX_ENABLE)) { in dp83822_read_status()
447 DP83822_FX_ENABLE | ctrl2); in dp83822_read_status()
A Dicplus.c351 u16 ctrl = 0, ctrl2 = 0; in ip101a_g_config_mdix() local
361 ctrl2 = IP101A_G_FORCE_MDIX; in ip101a_g_config_mdix()
379 IP101A_G_FORCE_MDIX, ctrl2); in ip101a_g_config_mdix()
/drivers/gpu/drm/bridge/analogix/
A Danalogix-i2c-dptx.c107 u8 ctrl2 = SP_AUX_EN; in anx_dp_aux_transfer() local
117 ctrl2 |= SP_ADDR_ONLY; in anx_dp_aux_transfer()
141 SP_ADDR_ONLY | SP_AUX_EN, ctrl2); in anx_dp_aux_transfer()
/drivers/gpu/drm/aspeed/
A Daspeed_gfx_crtc.c60 u32 ctrl2 = readl(priv->base + CRT_CTRL2); in aspeed_gfx_enable_controller() local
66 writel(ctrl2 | CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); in aspeed_gfx_enable_controller()
72 u32 ctrl2 = readl(priv->base + CRT_CTRL2); in aspeed_gfx_disable_controller() local
75 writel(ctrl2 & ~CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); in aspeed_gfx_disable_controller()
/drivers/net/ethernet/aquantia/atlantic/hw_atl/
A Dhw_atl_utils_fw2x.c418 u32 ctrl2, orig_ctrl2; in aq_fw2x_send_fw_request() local
432 ctrl2 = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); in aq_fw2x_send_fw_request()
433 orig_ctrl2 = ctrl2 & BIT(CAPS_HI_FW_REQUEST); in aq_fw2x_send_fw_request()
434 ctrl2 = ctrl2 ^ BIT(CAPS_HI_FW_REQUEST); in aq_fw2x_send_fw_request()
435 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, ctrl2); in aq_fw2x_send_fw_request()
/drivers/leds/
A Dleds-is31fl319x.c254 u8 ctrl1 = 0, ctrl2 = 0; in is31fl3196_brightness_set() local
283 ctrl2 |= on << (i - 6); /* 6..8 => bit 0..2 */ in is31fl3196_brightness_set()
286 if (ctrl1 > 0 || ctrl2 > 0) { in is31fl3196_brightness_set()
288 ctrl1, ctrl2); in is31fl3196_brightness_set()
290 regmap_write(is31->regmap, IS31FL3196_CTRL2, ctrl2); in is31fl3196_brightness_set()
/drivers/extcon/
A Dextcon-max14577.c198 u8 ctrl1, ctrl2 = 0; in max14577_muic_set_path() local
224 ctrl2 |= CTRL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ in max14577_muic_set_path()
226 ctrl2 |= CTRL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ in max14577_muic_set_path()
230 CTRL2_LOWPWR_MASK | CTRL2_CPEN_MASK, ctrl2); in max14577_muic_set_path()
238 ctrl1, ctrl2, attached ? "attached" : "detached"); in max14577_muic_set_path()
A Dextcon-max8997.c201 u8 ctrl1, ctrl2 = 0; in max8997_muic_set_path() local
216 ctrl2 |= CONTROL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ in max8997_muic_set_path()
218 ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ in max8997_muic_set_path()
221 MAX8997_MUIC_REG_CONTROL2, ctrl2, in max8997_muic_set_path()
230 ctrl1, ctrl2, attached ? "attached" : "detached"); in max8997_muic_set_path()
A Dextcon-max77843.c203 unsigned int ctrl1, ctrl2; in max77843_muic_set_path() local
225 ctrl2 = MAX77843_MUIC_CONTROL2_CPEN_MASK; in max77843_muic_set_path()
227 ctrl2 = MAX77843_MUIC_CONTROL2_LOWPWR_MASK; in max77843_muic_set_path()
232 MAX77843_MUIC_CONTROL2_CPEN_MASK, ctrl2); in max77843_muic_set_path()
240 ctrl1, ctrl2, attached ? "attached" : "detached"); in max77843_muic_set_path()
A Dextcon-max77693.c261 unsigned int ctrl1, ctrl2 = 0; in max77693_muic_set_path() local
276 ctrl2 |= MAX77693_CONTROL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ in max77693_muic_set_path()
278 ctrl2 |= MAX77693_CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ in max77693_muic_set_path()
283 ctrl2); in max77693_muic_set_path()
291 ctrl1, ctrl2, attached ? "attached" : "detached"); in max77693_muic_set_path()
/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
A Ddma.c202 __le32 ctrl2; /* buffer count and address extension */ member
303 return parity32(dd->addrlow ^ dd->addrhigh ^ dd->ctrl1 ^ dd->ctrl2); in dma64_dd_parity()
717 u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK; in dma64_dd_upd() local
724 ddring[outidx].ctrl2 = cpu_to_le32(ctrl2); in dma64_dd_upd()
732 ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE; in dma64_dd_upd()
736 ddring[outidx].ctrl2 = cpu_to_le32(ctrl2); in dma64_dd_upd()
740 ddring[outidx].ctrl2 = in dma64_dd_upd()
741 cpu_to_le32(ctrl2 | D64_CTRL2_PARITY); in dma64_dd_upd()
1508 (le32_to_cpu(di->txd64[i].ctrl2) & in dma_getnexttxp()
/drivers/tty/serial/
A Dmxs-auart.c946 u32 ctrl, ctrl2, div; in mxs_auart_settermios() local
952 ctrl2 = mxs_read(s, REG_CTRL2); in mxs_auart_settermios()
992 ctrl2 |= AUART_CTRL2_RXE; in mxs_auart_settermios()
994 ctrl2 &= ~AUART_CTRL2_RXE; in mxs_auart_settermios()
1001 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); in mxs_auart_settermios()
1013 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE in mxs_auart_settermios()
1018 ctrl2 |= AUART_CTRL2_RTSEN; in mxs_auart_settermios()
1020 ctrl2 |= AUART_CTRL2_CTSEN; in mxs_auart_settermios()
1041 mxs_write(ctrl2, s, REG_CTRL2); in mxs_auart_settermios()
/drivers/mmc/host/
A Dsdhci-pci-gli.c332 u16 ctrl2; in gli_set_9750() local
391 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
392 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; in gli_set_9750()
393 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
411 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
412 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; in gli_set_9750()
413 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
990 u16 ctrl2; in sdhci_gli_enable_internal_clock() local
992 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_gli_enable_internal_clock()
996 if (!((ctrl2 & SDHCI_CTRL_V4_MODE) && in sdhci_gli_enable_internal_clock()
[all …]
A Dsdhci.c129 u16 ctrl2; in sdhci_do_enable_v4_mode() local
131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
132 if (ctrl2 & SDHCI_CTRL_V4_MODE) in sdhci_do_enable_v4_mode()
135 ctrl2 |= SDHCI_CTRL_V4_MODE; in sdhci_do_enable_v4_mode()
136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
319 u16 ctrl2; in sdhci_config_dma() local
347 ctrl2 |= SDHCI_CTRL_64BIT_ADDR; in sdhci_config_dma()
1428 u16 ctrl2; in sdhci_auto_cmd_select() local
1442 ctrl2 |= SDHCI_CMD23_ENABLE; in sdhci_auto_cmd_select()
1444 ctrl2 &= ~SDHCI_CMD23_ENABLE; in sdhci_auto_cmd_select()
[all …]
/drivers/net/can/flexcan/
A Dflexcan-core.c234 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */ member
1292 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_set_bittiming_cbt()
1298 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_set_bittiming_cbt()
1371 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_ram_init()
1373 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_ram_init()
1381 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_ram_init()
1571 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_chip_start()
1573 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_chip_start()
1652 reg_ctrl2 = priv->read(&regs->ctrl2); in flexcan_chip_start()
1654 priv->write(reg_ctrl2, &regs->ctrl2); in flexcan_chip_start()
[all …]
/drivers/net/ethernet/stmicro/stmmac/
A Ddwmac4_core.c98 u32 ctrl2, ctrl3; in dwmac4_rx_queue_priority() local
101 ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2); in dwmac4_rx_queue_priority()
111 ctrl2 &= ~clear_mask; in dwmac4_rx_queue_priority()
118 ctrl2 |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & in dwmac4_rx_queue_priority()
121 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2); in dwmac4_rx_queue_priority()
130 writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2); in dwmac4_rx_queue_priority()

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